Always simulate both ETH tx and rx, no need to safe time by not simulating Rx...

Always simulate both ETH tx and rx, no need to safe time by not simulating Rx in case of UDP offlaod Tx only.

libraries/io/eth/src/vhdl/eth.vhd

@@ -638,7 +638,7 @@ BEGIN
     g_sim          => g_sim,
     g_sim_level    => g_sim_level,
     g_sim_tx       => TRUE,
-    g_sim_rx       => sel_a_b(g_sim_level=1, FALSE, TRUE) -- TX only when using fast behavioural model
+    g_sim_rx       => TRUE
   )
   PORT MAP (
     -- Clocks and reset