From 76b6827e421bfa1d63b2254fd2e278b3c1677895 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Tue, 25 Feb 2020 16:27:24 +0100
Subject: [PATCH] Always simulate both ETH tx and rx, no need to safe time by
not simulating Rx in case of UDP offlaod Tx only.
---
libraries/io/eth/src/vhdl/eth.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libraries/io/eth/src/vhdl/eth.vhd b/libraries/io/eth/src/vhdl/eth.vhd
index 3bc629d3d4..04dcd650ac 100644
--- a/libraries/io/eth/src/vhdl/eth.vhd
+++ b/libraries/io/eth/src/vhdl/eth.vhd
@@ -638,7 +638,7 @@ BEGIN
g_sim => g_sim,
g_sim_level => g_sim_level,
g_sim_tx => TRUE,
- g_sim_rx => sel_a_b(g_sim_level=1, FALSE, TRUE) -- TX only when using fast behavioural model
+ g_sim_rx => TRUE
)
PORT MAP (
-- Clocks and reset
--
GitLab