mm_clk frequency back to 50MHz (as it was before)

boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd

@@ -72,7 +72,7 @@ ARCHITECTURE str OF unb2_minimal IS
 
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2_board_fw_version := (1, 1);
-  CONSTANT c_mm_clk_freq            : NATURAL := c_unb2_board_mm_clk_freq_125M;
+  CONSTANT c_mm_clk_freq            : NATURAL := c_unb2_board_mm_clk_freq_50M;
 
   -- System
   SIGNAL cs_sim                     : STD_LOGIC;