Merge branch 'L2SDP-878' into 'master'

Resolve L2SDP-878

Closes L2SDP-878

See merge request desp/hdl!300

boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd

@@ -40,7 +40,7 @@
 -- > tc_unb2_test_eth_sim_stop.sh
 -- or use python script:
 -- . use -n 10000 packets/s to have 1 packet per BG sync interval of 100 us in sim
--- > tc_unb2_test_eth.py --gn2 0 --stream 0 -n 10000 --dest loopback --range 1000,1001,1 --interval 100 --scheme tx --sim
+-- > tc_unb2_test_eth.py --gn2 0 --stream 0 --dest loopback -r 10000 --sizes 1000 --interval 100 --scheme tx_rx --sim
 -- stop simulation.
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.ALL;

boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd

@@ -25,6 +25,7 @@
 -- Purpose: Tb to try loading design in simulator
 -- Description:
 -- Usage:
+-- > as 12
 -- > run 1 us.
 --
 -- Or try some MM:
@@ -32,6 +33,16 @@
 -- On command line do:
 -- > python $UPE_GEAR/peripherals/util_system_info.py --gn 0 -n 0 -v 5 --sim
 --
+-- To run BG eth_tester in simuation do:
+-- > run -a (or run 1 ms)
+-- . use -n 10000 packets/s to have 1 packet per BG sync interval of 100 us in sim
+-- > tc_unb2_test_eth.py --gn2 0 --stream 4 --dest loopback -r 10000 --sizes 1000 --interval 100 --scheme tx_rx --sim
+-- . stop simulation.
+--
+-- Remark:
+-- . To run with sim_tse or tech_tse use g_sim_level = 1 or 0 for u_eth_stream
+--   in unb2c_test. The tech_tse also models the MM setup. Default use sim_tse
+--   for faster sim.
 
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.ALL;
@@ -57,6 +68,8 @@ BEGIN
   eth_clk(0) <= NOT eth_clk(0) AFTER 8 ns;
   eth_clk(1) <= NOT eth_clk(1) AFTER 8 ns;
 
+  pps <= NOT pps AFTER 80 ns;
+
   eth_sgin <= eth_sgout;  -- loopback eth0 and eth1
 
   u_unb2c_test_1GbE_II : ENTITY work.unb2c_test_1GbE_II

boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd

@@ -914,7 +914,7 @@ BEGIN
     GENERIC MAP (
       g_technology   => g_technology,
       g_rx_udp_port  => TO_UINT(c_eth_rx_udp_port),  -- = 0x1771 = 6001
-      g_jumbo_en     => FALSE,
+      g_jumbo_en     => TRUE,
       g_sim          => g_sim,
       g_sim_level    => 1   -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
     )

boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml

@@ -128,8 +128,8 @@ peripherals:
     peripheral_group: eth1
     mm_port_names:
       - AVS_ETH_1_TSE
-      - AVS_ETH_1_REG  # not used for eth_stream
-      - AVS_ETH_1_RAM  # not used for eth_stream
+      - AVS_ETH_1_REG_NOT_USED  # not used for eth_stream
+      - AVS_ETH_1_RAM_NOT_USED  # not used for eth_stream
 
   - peripheral_name: diag/diag_block_gen
     peripheral_group: eth1_tx

libraries/io/eth/src/vhdl/eth_stream.vhd

@@ -53,7 +53,7 @@ ENTITY eth_stream IS
     g_technology   : NATURAL := c_tech_select_default;
     g_ETH_PHY      : STRING  := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
     g_rx_udp_port  : NATURAL := TO_UINT(c_eth_rx_udp_port);
-    g_jumbo_en     : BOOLEAN := FALSE;
+    g_jumbo_en     : BOOLEAN := TRUE;
     g_sim          : BOOLEAN := FALSE;
     g_sim_level    : NATURAL := 0   -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
   );
@@ -145,7 +145,7 @@ BEGIN
     mm_rst         => mm_rst,
     mm_clk         => mm_clk,   -- MM
     eth_clk        => eth_clk,  -- 125 MHz
-    tx_snk_clk     => st_rst,   -- DP
+    tx_snk_clk     => st_clk,   -- DP
     rx_src_clk     => st_clk,   -- DP
 
     -- TSE setup

libraries/technology/tse/tech_tse_setup.vhd

@@ -39,7 +39,7 @@ ENTITY tech_tse_setup IS
     -- = FALSE for frame_len <= 1500 octets. If frame is longer then this
     -- yields invalid length flag in rx_sosi.err, but data is still received.
     -- Use g_jumbo_en = TRUE for frame_len <= 9000 octets (jumbo frames).
-    g_jumbo_en : BOOLEAN := FALSE
+    g_jumbo_en : BOOLEAN := TRUE
   );
   PORT (
     -- Clocks and reset