diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
index 9b7ac16c162ae9800f67ce7d745287ff3580d3ce..c8060d477ab3092ab0b489485b04c01535daf4cc 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -40,7 +40,7 @@
-- > tc_unb2_test_eth_sim_stop.sh
-- or use python script:
-- . use -n 10000 packets/s to have 1 packet per BG sync interval of 100 us in sim
--- > tc_unb2_test_eth.py --gn2 0 --stream 0 -n 10000 --dest loopback --range 1000,1001,1 --interval 100 --scheme tx --sim
+-- > tc_unb2_test_eth.py --gn2 0 --stream 0 --dest loopback -r 10000 --sizes 1000 --interval 100 --scheme tx_rx --sim
-- stop simulation.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
index 42010cc38b4233a6194b5154a7aab5c2a65c6881..2f4584995ab62fc1b2a9ba16c4ef31fcdd54c1be 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
@@ -25,6 +25,7 @@
-- Purpose: Tb to try loading design in simulator
-- Description:
-- Usage:
+-- > as 12
-- > run 1 us.
--
-- Or try some MM:
@@ -32,6 +33,16 @@
-- On command line do:
-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 0 -n 0 -v 5 --sim
--
+-- To run BG eth_tester in simuation do:
+-- > run -a (or run 1 ms)
+-- . use -n 10000 packets/s to have 1 packet per BG sync interval of 100 us in sim
+-- > tc_unb2_test_eth.py --gn2 0 --stream 4 --dest loopback -r 10000 --sizes 1000 --interval 100 --scheme tx_rx --sim
+-- . stop simulation.
+--
+-- Remark:
+-- . To run with sim_tse or tech_tse use g_sim_level = 1 or 0 for u_eth_stream
+-- in unb2c_test. The tech_tse also models the MM setup. Default use sim_tse
+-- for faster sim.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
@@ -57,6 +68,8 @@ BEGIN
eth_clk(0) <= NOT eth_clk(0) AFTER 8 ns;
eth_clk(1) <= NOT eth_clk(1) AFTER 8 ns;
+ pps <= NOT pps AFTER 80 ns;
+
eth_sgin <= eth_sgout; -- loopback eth0 and eth1
u_unb2c_test_1GbE_II : ENTITY work.unb2c_test_1GbE_II
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index f584a6c375feb7ab4694d7e6fb1af511a3083148..6016c8f8e49bdbd148cd9f0842d16d1bb083ca7f 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -914,7 +914,7 @@ BEGIN
GENERIC MAP (
g_technology => g_technology,
g_rx_udp_port => TO_UINT(c_eth_rx_udp_port), -- = 0x1771 = 6001
- g_jumbo_en => FALSE,
+ g_jumbo_en => TRUE,
g_sim => g_sim,
g_sim_level => 1 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
)
diff --git a/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml b/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml
index 0c7f07d961f8ea77e4da22f3a53b55003d482881..52079ec548029f726c6dd31f361e7db65f14c929 100644
--- a/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml
+++ b/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml
@@ -128,8 +128,8 @@ peripherals:
peripheral_group: eth1
mm_port_names:
- AVS_ETH_1_TSE
- - AVS_ETH_1_REG # not used for eth_stream
- - AVS_ETH_1_RAM # not used for eth_stream
+ - AVS_ETH_1_REG_NOT_USED # not used for eth_stream
+ - AVS_ETH_1_RAM_NOT_USED # not used for eth_stream
- peripheral_name: diag/diag_block_gen
peripheral_group: eth1_tx
diff --git a/libraries/io/eth/src/vhdl/eth_stream.vhd b/libraries/io/eth/src/vhdl/eth_stream.vhd
index ea47c91393a4503900bef921d609bd7a13e26283..848ed7e23f3e4e6d3c222f67b820c6e6345d805d 100644
--- a/libraries/io/eth/src/vhdl/eth_stream.vhd
+++ b/libraries/io/eth/src/vhdl/eth_stream.vhd
@@ -53,7 +53,7 @@ ENTITY eth_stream IS
g_technology : NATURAL := c_tech_select_default;
g_ETH_PHY : STRING := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
g_rx_udp_port : NATURAL := TO_UINT(c_eth_rx_udp_port);
- g_jumbo_en : BOOLEAN := FALSE;
+ g_jumbo_en : BOOLEAN := TRUE;
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
);
@@ -145,7 +145,7 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk, -- MM
eth_clk => eth_clk, -- 125 MHz
- tx_snk_clk => st_rst, -- DP
+ tx_snk_clk => st_clk, -- DP
rx_src_clk => st_clk, -- DP
-- TSE setup
diff --git a/libraries/technology/tse/tech_tse_setup.vhd b/libraries/technology/tse/tech_tse_setup.vhd
index fc02da2dc47117ca8647e27f75e60cd68577433b..f3b4fd0d8d5b6f84c7b73a0f160b9921011d057d 100644
--- a/libraries/technology/tse/tech_tse_setup.vhd
+++ b/libraries/technology/tse/tech_tse_setup.vhd
@@ -39,7 +39,7 @@ ENTITY tech_tse_setup IS
-- = FALSE for frame_len <= 1500 octets. If frame is longer then this
-- yields invalid length flag in rx_sosi.err, but data is still received.
-- Use g_jumbo_en = TRUE for frame_len <= 9000 octets (jumbo frames).
- g_jumbo_en : BOOLEAN := FALSE
+ g_jumbo_en : BOOLEAN := TRUE
);
PORT (
-- Clocks and reset