SVN move

libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg

+hdl_lib_name = unb1_fn_bf
+hdl_library_clause_name = unb1_fn_bf_lib
+hdl_lib_uses_synth = common technology mm i2c unb1_board bf
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_top_level_entity =
+
+synth_files =   
+    $HDL_BUILD_DIR/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
+    src/vhdl/mmm_unb1_fn_bf.vhd
+    src/vhdl/node_unb1_fn_bf.vhd
+    src/vhdl/unb1_fn_bf.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_unb1_fn_bf.vhd
+
+modelsim_copy_files = src/hex hex                                                   
+
+quartus_copy_files = quartus/sopc_unb1_fn_bf.sopc .
+
+quartus_qsf_files =                                                       
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+    ../../libraries/dsp/bf/src/tcl/bf_constraints.tcl  
+    quartus/unb1_fn_bf_pins.tcl
+    
+quartus_qip_files =
+    $HDL_BUILD_DIR/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
+

libraries/dsp/bf/designs/unb1_fn_bf/quartus/unb1_fn_bf_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+

libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, diag_lib, eth_lib, tech_tse_lib, bf_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE eth_lib.eth_pkg.ALL; 
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+USE bf_lib.ALL;
+USE bf_lib.bf_pkg.ALL;
+
+ENTITY node_unb1_fn_bf IS
+  GENERIC(
+    g_use_bf                : BOOLEAN  := TRUE; -- FALSE skips instantiation of the BF
+    g_bf                    : t_c_bf   := c_bf;
+    g_bf_weights_file_name  : STRING   := "../../../../../dsp/bf/build/data/weights";              -- default file location for synthesis
+    g_ss_wide_file_prefix   : STRING   := "UNUSED"; -- path_to_file    
+    g_bf_offload            : BOOLEAN  := FALSE; -- Use DP TX offload to stream BF output towards LCU
+    g_use_block_gen         : BOOLEAN  := TRUE;  -- FALSE uses external input.
+    g_block_gen_file_prefix : STRING   := "../../../../../modules/Lofar/diag/src/data/bf_in_data"; -- default file location for synthesis
+    g_bg_diag_wave_period   : POSITIVE := 4;     -- This generic defines the period of the waveform that is generated with the block generator.  
+    g_weights_write_only    : BOOLEAN  := FALSE     -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+  );
+  PORT(
+    -- System
+    mm_rst                  : IN  STD_LOGIC;
+    mm_clk                  : IN  STD_LOGIC;   -- 125 MHz from xo_clk PLL in SOPC system
+    dp_rst                  : IN  STD_LOGIC;
+    dp_clk                  : IN  STD_LOGIC;   -- 200 MHz from CLK system clock
+    -- MM interface         
+    -- . block generator    
+    reg_diag_bg_mosi        : IN  t_mem_mosi; 
+    reg_diag_bg_miso        : OUT t_mem_miso; 
+    ram_diag_bg_mosi        : IN  t_mem_mosi; 
+    ram_diag_bg_miso        : OUT t_mem_miso; 
+    -- . beam former       
+    ram_ss_ss_wide_mosi     : IN  t_mem_mosi;
+    ram_ss_ss_wide_miso     : OUT t_mem_miso := c_mem_miso_rst;  
+    ram_bf_weights_mosi     : IN  t_mem_mosi;
+    ram_bf_weights_miso     : OUT t_mem_miso; 
+    ram_st_sst_bf_mosi      : IN  t_mem_mosi;
+    ram_st_sst_bf_miso      : OUT t_mem_miso;
+    reg_st_sst_bf_mosi      : IN  t_mem_mosi;
+    reg_st_sst_bf_miso      : OUT t_mem_miso;
+    -- . hdr_insert and hdr_remove for bf_out_offload
+    reg_hdr_insert_mosi     : IN  t_mem_mosi := c_mem_mosi_rst;
+    ram_hdr_insert_mosi     : IN  t_mem_mosi := c_mem_mosi_rst;
+    -- . Nof words to offload selection
+    reg_dp_split_mosi       : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_dp_split_miso       : OUT t_mem_miso;
+    reg_dp_pkt_merge_mosi   : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_dp_pkt_merge_miso   : OUT t_mem_miso;
+
+    -- ST interface, BF subbands in
+    ext_in_sosi_arr         : IN  t_dp_sosi_arr( g_bf.nof_input_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst); 
+    ext_in_siso_arr         : OUT t_dp_siso_arr( g_bf.nof_input_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rst);     
+
+    -- ST interface, BF beamlets out
+    out_raw_sosi_arr        : OUT t_dp_sosi_arr( g_bf.nof_bf_units-1 DOWNTO 0);  -- raw beamlets
+    out_bst_sosi_arr        : OUT t_dp_sosi_arr( g_bf.nof_bf_units-1 DOWNTO 0);  -- 16b beamlets; a selection can be offloaded via bf_out_offload_tx_sosi_arr.
+    out_qua_sosi_arr        : OUT t_dp_sosi_arr( g_bf.nof_bf_units-1 DOWNTO 0);  --  8b beamlets
+
+    -- DP offload for 1GbE
+    bf_out_offload_tx_sosi_arr : OUT t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);  -- 16b beamlets
+    bf_out_offload_tx_siso_arr : IN  t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst)
+  );
+END node_unb1_fn_bf;
+
+ARCHITECTURE str OF node_unb1_fn_bf IS   
+  
+  CONSTANT c_buf_addr_w     : NATURAL  := ceil_log2(g_bg_diag_wave_period) + ceil_log2(g_bf.nof_subbands*g_bf.nof_signal_paths/g_bf.nof_input_streams);
+  
+  SIGNAL bf_in_sosi_arr     : t_dp_sosi_arr( g_bf.nof_input_streams-1 DOWNTO 0); 
+  SIGNAL bg_out_sosi_arr    : t_dp_sosi_arr( g_bf.nof_input_streams-1 DOWNTO 0); 
+
+  SIGNAL i_out_bst_sosi_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
+  
+BEGIN
+
+  out_bst_sosi_arr <= i_out_bst_sosi_arr;
+
+  ---------------------------------------------------------------------------------------
+  -- Use Block Generator input by default
+  ---------------------------------------------------------------------------------------              
+  gen_block_gen : IF g_use_block_gen = TRUE GENERATE
+    u_bg : ENTITY diag_lib.mms_diag_block_gen 
+    GENERIC MAP(    
+      g_blk_sync           => TRUE,
+      g_nof_output_streams => g_bf.nof_input_streams,
+      g_buf_dat_w          => c_nof_complex*g_bf.in_dat_w, 
+      g_buf_addr_w         => c_buf_addr_w,              -- Waveform buffer size 2**g_buf_addr_w nof samples
+      g_file_name_prefix   => g_block_gen_file_prefix
+    )
+    PORT MAP(
+      -- System
+      mm_rst           => mm_rst, 
+      mm_clk           => mm_clk, 
+      dp_rst           => dp_rst, 
+      dp_clk           => dp_clk,
+      -- MM interface
+      reg_bg_ctrl_mosi => reg_diag_bg_mosi, 
+      reg_bg_ctrl_miso => reg_diag_bg_miso, 
+      ram_bg_data_mosi => ram_diag_bg_mosi, 
+      ram_bg_data_miso => ram_diag_bg_miso, 
+      -- ST interface
+      out_sosi_arr     => bg_out_sosi_arr
+    );
+    
+    bf_in_sosi_arr <= bg_out_sosi_arr;
+  END GENERATE;
+
+  ---------------------------------------------------------------------------------------
+  -- Override Block Generator output and use external input instead
+  ---------------------------------------------------------------------------------------              
+  gen_ext_in : IF g_use_block_gen = FALSE GENERATE
+    bf_in_sosi_arr <= ext_in_sosi_arr;
+  END GENERATE;
+
+  ---------------------------------------------------------------------------------------
+  -- Beam Former
+  ---------------------------------------------------------------------------------------  
+  gen_bf : IF g_use_bf = TRUE GENERATE
+    u_bf : ENTITY bf_lib.bf 
+    GENERIC MAP (
+      g_bf                    => g_bf,
+      g_bf_weights_file_name  => g_bf_weights_file_name,
+      g_ss_wide_file_prefix   => g_ss_wide_file_prefix,   
+      g_weights_write_only    => g_weights_write_only
+    )
+    PORT MAP ( 
+      -- System
+      dp_rst                  =>  dp_rst,
+      dp_clk                  =>  dp_clk,
+      mm_rst                  =>  mm_rst,
+      mm_clk                  =>  mm_clk,
+      
+      -- MM interface
+      ram_ss_ss_wide_mosi     => ram_ss_ss_wide_mosi,
+      ram_ss_ss_wide_miso     => ram_ss_ss_wide_miso,  
+      ram_bf_weights_mosi     => ram_bf_weights_mosi,
+      ram_bf_weights_miso     => ram_bf_weights_miso,
+      ram_st_sst_mosi         => ram_st_sst_bf_mosi,
+      ram_st_sst_miso         => ram_st_sst_bf_miso,
+      reg_st_sst_mosi         => reg_st_sst_bf_mosi,
+      reg_st_sst_miso         => reg_st_sst_bf_miso,
+      
+      -- ST interface
+      in_sosi_arr             => bf_in_sosi_arr,  
+      in_siso_arr             => ext_in_siso_arr,  
+      
+      out_raw_sosi_arr        => out_raw_sosi_arr,    -- raw beamlets
+      out_bst_sosi_arr        => i_out_bst_sosi_arr,  -- 16b beamlets
+      out_qua_sosi_arr        => out_qua_sosi_arr     --  8b beamlets
+    ); 
+  END GENERATE;
+
+  ---------------------------------------------------------------------------------------
+  -- Offload 16b beamlets from out_bst_sosi_arr to udp_offload TX port in ctrl_unb_common
+  ---------------------------------------------------------------------------------------           
+  gen_bf_offload : IF g_bf_offload = TRUE GENERATE
+    u_dp_offload : ENTITY dp_lib.dp_offload_tx
+    GENERIC MAP (
+      g_nof_streams         => g_bf.nof_bf_units,
+      g_data_w              => c_eth_data_w,
+      g_block_size          => g_bf.nof_weights,  -- = 256
+      g_block_nof_sel_words => 20,
+      g_nof_words_per_pkt   => 360,
+      g_hdr_nof_words       => c_network_total_header_32b_nof_words,
+      g_use_complex         => TRUE,
+      g_use_input_fifo      => TRUE,
+      g_use_output_fifo     => TRUE
+    )
+    PORT MAP (
+      mm_rst                => mm_rst,
+      mm_clk                => mm_clk,
+      
+      st_rst                => dp_rst,
+      st_clk                => dp_clk,
+  
+      reg_hdr_insert_mosi   => reg_hdr_insert_mosi,
+      ram_hdr_insert_mosi   => ram_hdr_insert_mosi,
+      reg_dp_split_mosi     => reg_dp_split_mosi,    
+      reg_dp_split_miso     => reg_dp_split_miso,
+      reg_dp_pkt_merge_mosi => reg_dp_pkt_merge_mosi,    
+      reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso,
+  
+      dp_sosi_arr           => i_out_bst_sosi_arr,
+      dp_siso_arr           => OPEN, -- No flow control, so we're instantiating an input FIFO.
+  
+      tx_sosi_arr           => bf_out_offload_tx_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0),
+      tx_siso_arr           => bf_out_offload_tx_siso_arr(g_bf.nof_bf_units-1 DOWNTO 0)
+    );
+  END GENERATE;                                            
+  
+END str;

libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd

+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, bf_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+USE bf_lib.bf_pkg.ALL;
+
+ENTITY unb1_fn_bf IS
+  GENERIC (
+    g_design_name : STRING  := "unb1_fn_bf";
+    g_design_note : STRING  := "UNUSED";
+    g_sim         : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_unb_nr  : NATURAL := 0;
+    g_sim_node_nr : NATURAL := 0;
+    g_stamp_date  : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time  : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_stamp_svn   : NATURAL := 0;  -- SVN revision    -- set by QSF
+    g_bf          : t_c_bf  := c_bf 
+  );
+  PORT (
+   -- GENERAL
+    CLK           : IN    STD_LOGIC; -- System Clock
+    PPS           : IN    STD_LOGIC; -- System Sync
+    WDI           : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA          : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB          : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION       : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+    ID            : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+    TESTIO        : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+    
+    -- I2C Interface to Sensors
+    sens_sc       : INOUT STD_LOGIC;
+    sens_sd       : INOUT STD_LOGIC;
+
+    -- 1GbE Control Interface
+    ETH_clk       : IN    STD_LOGIC;
+    ETH_SGIN      : IN    STD_LOGIC;
+    ETH_SGOUT     : OUT   STD_LOGIC
+  );
+END unb1_fn_bf;
+
+
+ARCHITECTURE str OF unb1_fn_bf IS   
+
+  
+  CONSTANT c_bf_offload            : BOOLEAN := FALSE; -- Offload BF out(0) datapath to 1GbE UDP TX port
+  CONSTANT c_use_phy               : t_c_unb1_board_use_phy := (1, 0, 0, 0, 0, 0, 0, 1); 
+  CONSTANT c_fw_version            : t_unb1_board_fw_version := (2, 3);  -- firmware version x.y
+  CONSTANT c_nof_streams           : NATURAL := c_eth_nof_udp_ports;
+  CONSTANT c_weights_write_only    : BOOLEAN := TRUE; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+  
+  -- Use default RAM inti files. The RAM init file for simulation lies one ../ level further way then for synthesis
+  CONSTANT c_bf_weights_file_name  : STRING := "UNUSED";   
+  CONSTANT c_ss_wide_file_prefix   : STRING := "hex/ss_wide";   
+  CONSTANT c_block_gen_file_prefix : STRING := "UNUSED";
+    
+    -- BF offload                                                                                                       
+  CONSTANT c_hdr_nof_words          : NATURAL := c_network_total_header_32b_nof_words;
+  CONSTANT c_dp_ram_mm_nof_words    : NATURAL := c_hdr_nof_words * (c_eth_data_w/c_word_w);
+  CONSTANT c_dp_ram_mm_adr_w        : NATURAL := ceil_log2(c_dp_ram_mm_nof_words);
+        
+  -- System
+  SIGNAL cs_sim                     : STD_LOGIC;
+  SIGNAL xo_clk                     : STD_LOGIC;
+  SIGNAL xo_rst                     : STD_LOGIC;
+  SIGNAL xo_rst_n                   : STD_LOGIC;
+  SIGNAL mm_clk                     : STD_LOGIC;
+  SIGNAL mm_locked                  : STD_LOGIC;
+  SIGNAL mm_rst                     : STD_LOGIC;
+  
+  SIGNAL dp_rst                     : STD_LOGIC;
+  SIGNAL dp_clk                     : STD_LOGIC;
+  SIGNAL dp_pps                     : STD_LOGIC;
+  
+  SIGNAL app_led_red                : STD_LOGIC := '0';
+  SIGNAL app_led_green              : STD_LOGIC := '1';
+  
+  -- PIOs
+  SIGNAL pout_wdi                   : STD_LOGIC;
+
+  -- WDI override
+  SIGNAL reg_wdi_mosi               : t_mem_mosi;
+  SIGNAL reg_wdi_miso               : t_mem_miso;
+
+  -- PPSH
+  SIGNAL reg_ppsh_mosi              : t_mem_mosi;
+  SIGNAL reg_ppsh_miso              : t_mem_miso;
+  
+  -- UniBoard system info
+  SIGNAL reg_unb_system_info_mosi   : t_mem_mosi;
+  SIGNAL reg_unb_system_info_miso   : t_mem_miso;
+  SIGNAL rom_unb_system_info_mosi   : t_mem_mosi;
+  SIGNAL rom_unb_system_info_miso   : t_mem_miso;
+
+  -- eth1g
+  SIGNAL eth1g_tse_clk              : STD_LOGIC;
+  SIGNAL eth1g_mm_rst               : STD_LOGIC;
+  SIGNAL eth1g_tse_mosi             : t_mem_mosi := c_mem_mosi_rst;  -- ETH TSE MAC registers
+  SIGNAL eth1g_tse_miso             : t_mem_miso;
+  SIGNAL eth1g_reg_mosi             : t_mem_mosi := c_mem_mosi_rst;  -- ETH control and status registers
+  SIGNAL eth1g_reg_miso             : t_mem_miso;
+  SIGNAL eth1g_reg_interrupt        : STD_LOGIC;   -- Interrupt
+  SIGNAL eth1g_ram_mosi             : t_mem_mosi := c_mem_mosi_rst;  -- ETH rx frame and tx frame memory
+  SIGNAL eth1g_ram_miso             : t_mem_miso;
+  SIGNAL eth1g_led                  : t_tech_tse_led;
+
+  -- eth1g UDP streaming ports
+  SIGNAL eth1g_udp_tx_sosi_arr      : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
+  SIGNAL eth1g_udp_tx_siso_arr      : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0);  
+  
+  -- MM registers and RAM
+  -- . block generator
+  SIGNAL reg_diag_bg_mosi           : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_diag_bg_miso           : t_mem_miso;  
+  SIGNAL ram_diag_bg_mosi           : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_diag_bg_miso           : t_mem_miso;                  
+  -- . beam former
+  SIGNAL ram_bf_weights_mosi        : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_bf_weights_miso        : t_mem_miso;                  
+  SIGNAL ram_st_sst_bf_mosi         : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_st_sst_bf_miso         : t_mem_miso;                  
+  SIGNAL reg_st_sst_bf_mosi         : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_st_sst_bf_miso         : t_mem_miso;                  
+  SIGNAL ram_ss_ss_wide_mosi        : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_ss_ss_wide_miso        : t_mem_miso;                  
+
+  -- . uniboard sensors
+  SIGNAL reg_unb_sens_mosi          : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_unb_sens_miso          : t_mem_miso;                  
+
+ 
+  SIGNAL reg_diagnostics_mosi       : t_mem_mosi;
+  SIGNAL reg_diagnostics_miso       : t_mem_miso;
+  -- . dp_ram_from_mm for DP offload (header insertion)
+  SIGNAL reg_dp_ram_from_mm_mosi    : t_mem_mosi;
+  SIGNAL reg_dp_ram_from_mm_miso    : t_mem_miso := c_mem_miso_rst;
+
+  SIGNAL ram_dp_ram_from_mm_mosi    : t_mem_mosi;
+  SIGNAL ram_dp_ram_from_mm_miso    : t_mem_miso := c_mem_miso_rst;
+
+  SIGNAL ram_dp_ram_to_mm_mosi      : t_mem_mosi;
+  SIGNAL ram_dp_ram_to_mm_miso      : t_mem_miso;
+
+  SIGNAL reg_dp_split_mosi          : t_mem_mosi;
+  SIGNAL reg_dp_split_miso          : t_mem_miso;
+
+  SIGNAL reg_dp_pkt_merge_mosi      : t_mem_mosi;
+  SIGNAL reg_dp_pkt_merge_miso      : t_mem_miso;
+                                    
+  -- ST interface
+  SIGNAL beams_sosi_arr             : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
+  
+BEGIN
+  
+  -----------------------------------------------------------------------------
+  -- General control function
+  -----------------------------------------------------------------------------
+  u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
+  GENERIC MAP (
+    g_sim           => g_sim,
+    g_design_name   => g_design_name,
+    g_design_note   => g_design_note,
+    g_stamp_date    => g_stamp_date,
+    g_stamp_time    => g_stamp_time, 
+    g_stamp_svn     => g_stamp_svn, 
+    g_fw_version    => c_fw_version,
+    g_mm_clk_freq   => c_unb1_board_mm_clk_freq_50M,
+    g_use_phy       => c_use_phy,
+    g_udp_offload   => sel_a_b(c_bf_offload, TRUE, FALSE),
+    g_aux           => c_unb1_board_aux,
+    g_udp_offload_nof_streams => c_nof_streams
+  )
+  PORT MAP (
+    -- Clock an reset signals
+    cs_sim                   => cs_sim,
+    xo_clk                   => xo_clk,
+    xo_rst                   => xo_rst,
+    xo_rst_n                 => xo_rst_n,
+
+    mm_clk                   => mm_clk,
+    mm_locked                => mm_locked,
+    mm_rst                   => mm_rst,
+
+    dp_rst                   => dp_rst,
+    dp_clk                   => dp_clk,
+    dp_pps                   => OPEN,
+    dp_rst_in                => dp_rst,
+    dp_clk_in                => dp_clk,
+    
+    -- Toggle WDI
+    pout_wdi                 => pout_wdi,
+
+    -- MM buses
+    -- . Manual WDI override
+    reg_wdi_mosi             => reg_wdi_mosi,
+    reg_wdi_miso             => reg_wdi_miso,
+    
+    -- . System_info
+    reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+    reg_unb_system_info_miso => reg_unb_system_info_miso, 
+    rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+    rom_unb_system_info_miso => rom_unb_system_info_miso, 
+    
+    -- . UniBoard I2C sensors
+    reg_unb_sens_mosi        => reg_unb_sens_mosi,
+    reg_unb_sens_miso        => reg_unb_sens_miso,    
+    
+    -- . PPSH
+    reg_ppsh_mosi            => reg_ppsh_mosi,
+    reg_ppsh_miso            => reg_ppsh_miso,
+    
+    -- eth1g
+    eth1g_tse_clk            => eth1g_tse_clk,   -- 125 MHz from xo_clk PLL in SOPC system
+    eth1g_mm_rst             => eth1g_mm_rst,
+    eth1g_tse_mosi           => eth1g_tse_mosi,
+    eth1g_tse_miso           => eth1g_tse_miso,
+    eth1g_reg_mosi           => eth1g_reg_mosi,
+    eth1g_reg_miso           => eth1g_reg_miso,
+    eth1g_reg_interrupt      => eth1g_reg_interrupt,
+    eth1g_ram_mosi           => eth1g_ram_mosi,
+    eth1g_ram_miso           => eth1g_ram_miso,
+
+    -- eth1g UDP streaming ports to offload BF out
+    udp_tx_sosi_arr        =>  eth1g_udp_tx_sosi_arr,
+    udp_tx_siso_arr        =>  eth1g_udp_tx_siso_arr,
+        
+    -- FPGA pins
+    -- . General
+    CLK                      => CLK,
+    PPS                      => PPS,
+    WDI                      => WDI,
+    INTA                     => INTA,
+    INTB                     => INTB,
+    -- . Others
+    VERSION                  => VERSION,
+    ID                       => ID,
+    TESTIO                   => TESTIO,
+    -- . I2C Interface to Sensors
+    sens_sc                  => sens_sc,
+    sens_sd                  => sens_sd,        
+    -- . 1GbE Control Interface
+    ETH_clk                  => ETH_clk,
+    ETH_SGIN                 => ETH_SGIN,
+    ETH_SGOUT                => ETH_SGOUT
+  );
+  
+  
+  -----------------------------------------------------------------------------
+  -- MM master
+  -----------------------------------------------------------------------------
+  u_mmm : ENTITY work.mmm_fn_bf
+  GENERIC MAP (
+    g_sim         => g_sim,
+    g_sim_unb_nr  => g_sim_unb_nr,
+    g_sim_node_nr => g_sim_node_nr,
+    g_bf          => g_bf
+   )
+  PORT MAP(  
+    xo_clk                   => xo_clk,       
+    xo_rst_n                 => xo_rst_n,     
+    xo_rst                   => xo_rst,       
+
+    mm_rst                   => mm_rst,
+    mm_clk                   => mm_clk,       
+    mm_locked                => mm_locked,    
+
+    -- PIOs
+    pout_wdi                 => pout_wdi,
+
+    -- Manual WDI override
+    reg_wdi_mosi             => reg_wdi_mosi,
+    reg_wdi_miso             => reg_wdi_miso,
+
+    -- system_info
+    reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+    reg_unb_system_info_miso => reg_unb_system_info_miso,
+    rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+    rom_unb_system_info_miso => rom_unb_system_info_miso, 
+
+    -- UniBoard I2C sensors
+    reg_unb_sens_mosi        => reg_unb_sens_mosi,
+    reg_unb_sens_miso        => reg_unb_sens_miso, 
+ 
+    -- eth1g
+    eth1g_tse_clk            => eth1g_tse_clk,
+    eth1g_mm_rst             => eth1g_mm_rst,
+    eth1g_tse_mosi           => eth1g_tse_mosi,
+    eth1g_tse_miso           => eth1g_tse_miso,
+    eth1g_reg_mosi           => eth1g_reg_mosi,
+    eth1g_reg_miso           => eth1g_reg_miso,
+    eth1g_reg_interrupt      => eth1g_reg_interrupt,
+    eth1g_ram_mosi           => eth1g_ram_mosi,
+    eth1g_ram_miso           => eth1g_ram_miso,
+
+    -- Diagnostics
+    reg_diagnostics_mosi     => reg_diagnostics_mosi, 
+    reg_diagnostics_miso     => reg_diagnostics_miso,   
+    
+    -- . block generator
+    reg_diag_bg_mosi         => reg_diag_bg_mosi,
+    reg_diag_bg_miso         => reg_diag_bg_miso,
+    ram_diag_bg_mosi         => ram_diag_bg_mosi,
+    ram_diag_bg_miso         => ram_diag_bg_miso,
+    
+    -- beamformer
+    ram_ss_ss_wide_mosi      => ram_ss_ss_wide_mosi,
+    ram_ss_ss_wide_miso      => ram_ss_ss_wide_miso,  
+    ram_bf_weights_mosi      => ram_bf_weights_mosi,
+    ram_bf_weights_miso      => ram_bf_weights_miso,
+    ram_st_sst_bf_mosi       => ram_st_sst_bf_mosi,
+    ram_st_sst_bf_miso       => ram_st_sst_bf_miso,
+    reg_st_sst_bf_mosi       => reg_st_sst_bf_mosi,
+    reg_st_sst_bf_miso       => reg_st_sst_bf_miso,
+                                                        
+    -- dp_offload               -- dp_offload           
+    reg_dp_ram_from_mm_mosi  => reg_dp_ram_from_mm_mosi,
+    reg_dp_ram_from_mm_miso  => reg_dp_ram_from_mm_miso,
+    ram_dp_ram_from_mm_mosi  => ram_dp_ram_from_mm_mosi,
+    ram_dp_ram_from_mm_miso  => ram_dp_ram_from_mm_miso,
+    reg_dp_split_mosi        => reg_dp_split_mosi, 
+    reg_dp_split_miso        => reg_dp_split_miso,
+    reg_dp_pkt_merge_mosi    => reg_dp_pkt_merge_mosi,
+    reg_dp_pkt_merge_miso    => reg_dp_pkt_merge_miso
+  );
+  
+  u_node_unb1_fn_bf : ENTITY work.node_unb1_fn_bf
+  GENERIC MAP(
+    g_bf                    => g_bf,
+    g_bf_offload            => c_bf_offload,
+    g_bf_weights_file_name  => c_bf_weights_file_name,
+    g_ss_wide_file_prefix   => c_ss_wide_file_prefix,  
+    g_block_gen_file_prefix => c_block_gen_file_prefix,
+    g_weights_write_only    => c_weights_write_only
+  )
+  PORT MAP(
+    -- System
+    mm_rst                  => mm_rst, 
+    mm_clk                  => mm_clk, 
+    dp_rst                  => dp_rst, 
+    dp_clk                  => dp_clk, 
+    -- MM interface
+    -- . block generator
+    reg_diag_bg_mosi        => reg_diag_bg_mosi,  
+    reg_diag_bg_miso        => reg_diag_bg_miso,
+    ram_diag_bg_mosi        => ram_diag_bg_mosi,  
+    ram_diag_bg_miso        => ram_diag_bg_miso,  
+    
+    -- . beam former        
+    ram_bf_weights_mosi     => ram_bf_weights_mosi,   
+    ram_bf_weights_miso     => ram_bf_weights_miso,   
+    ram_ss_ss_wide_mosi     => ram_ss_ss_wide_mosi,   
+    ram_ss_ss_wide_miso     => ram_ss_ss_wide_miso,   
+    ram_st_sst_bf_mosi      => ram_st_sst_bf_mosi,      
+    ram_st_sst_bf_miso      => ram_st_sst_bf_miso,
+    reg_st_sst_bf_mosi      => reg_st_sst_bf_mosi,      
+    reg_st_sst_bf_miso      => reg_st_sst_bf_miso,
+
+    -- . hdr_insert for dp offload
+    reg_hdr_insert_mosi     => reg_dp_ram_from_mm_mosi,
+    ram_hdr_insert_mosi     => ram_dp_ram_from_mm_mosi,
+                            
+    -- ST interface         
+    out_bst_sosi_arr        => OPEN,            -- 16b beamlets
+    out_qua_sosi_arr        => beams_sosi_arr,  --  8b beamlets
+
+    -- DP offload of 16b beamlets to 1GbE via ctrl_unb_common
+    bf_out_offload_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+    bf_out_offload_tx_siso_arr => eth1g_udp_tx_siso_arr
+  );
+END;
+    
+    
+    
+    
+             
+             
+             
+             
+             
+             
+             
+             
+             

libraries/dsp/bf/designs/unb1_fn_bf/tb/python/tc_unb1_fn_bf.py

+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2012
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for the fn_bf design
+
+   Usage: python tc_unb1_fn_bf.py --unb 0 --fn 0:3 --rep 1 -n 1 -v 6
+
+"""
+
+###############################################################################
+# System imports
+import sys
+import test_case
+import node_io
+import pi_unb_sens
+import pi_diag_block_gen
+import pi_bf_bf
+import pi_st_sst
+import pi_ss_ss_wide
+import unb_apertif as apr
+from tools import *
+from common import * 
+import mem_init_file
+
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+tc.set_result('PASSED')
+tc.append_log(3, '>>>')
+tc.append_log(1, '>>> Title : Test case for the fn_bf design on %s' % tc.unb_nodes_string())
+tc.append_log(3, '>>>')
+tc.append_log(3, '')
+
+# Constants/Generics that are shared between VHDL and Python
+# Name                   Value   Default   Description
+# START_VHDL_GENERICS
+c_nof_signal_paths     = 16      # 64
+c_nof_input_streams    =  4      # 16 
+c_nof_subbands         = 24      # 24
+c_nof_weights          = 256      # 256
+c_nof_bf_units         =  4      # 4
+c_in_dat_w             = 16      # 16
+c_in_weight_w          = 16      # 16
+c_gain_w               = -1      # -1
+c_bst_dat_w            = 16      # 16                                
+c_bst_lsb_w            = 14      # 14
+c_out_dat_w            = 39      # 8 for the correlator, 16 for udp_offload, 39 for capturein databuffer of testbench
+c_out_lsb_w            = 14      # 14
+c_stat_data_w          = 56      # 56
+c_stat_data_sz         =  2      # 2
+c_bf_weights_file_name = "../../../build/data/weights" #  -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
+# END_VHDL_GENERICS    
+
+c_blocks_per_sync      = 100
+c_clk_period           = 1  # ns
+# Overrule constant definitions when testcase runs on hardware. 
+if tc.sim==False:
+    c_nof_signal_paths     = 64
+    c_nof_input_streams    = 16 
+    c_nof_subbands         = 24
+    c_nof_weights          = 256
+    c_nof_bf_units         = 4
+    c_in_dat_w             = 16
+    c_in_weight_w          = 16
+    c_gain_w               = -1
+    c_bst_dat_w            = 16                                
+    c_bst_lsb_w            = 14
+    c_out_dat_w            = 39  # 8 for the correlator, 16 for udp_offload, 39 for capturein databuffer of testbench
+    c_out_lsb_w            = 14
+    c_stat_data_w          = 56
+    c_stat_data_sz         = 2
+    c_bf_weights_file_name = "../../../build/data/weights" #  -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
+    c_blocks_per_sync      = 781250
+
+c_nof_sp_per_input_stream = c_nof_signal_paths / c_nof_input_streams
+c_nof_subbands_per_stream = c_nof_subbands*c_nof_sp_per_input_stream 
+
+# Define settings for the block generator
+c_samples_per_packet = c_nof_sp_per_input_stream * c_nof_subbands
+c_gapsize            = c_nof_weights - c_samples_per_packet
+c_mem_low_addr       = 0
+c_mem_high_addr      = c_samples_per_packet-1
+c_bsn_init           = 42     
+c_gen_hex_files      = True
+    
+# Create access object for all nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+# Create instances for the block generator (BG)
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, nofChannels=c_nof_input_streams, ramSizePerChannel= 4*2**(ceil_log2(c_samples_per_packet)))
+
+# Create instances for the beamformer units (BF)
+bf=[]   
+for i in range(tc.nofFnNodes):
+    for j in xrange(c_nof_bf_units):
+        bf.append(pi_bf_bf.PiBfBf(tc, io, c_nof_weights, c_nof_signal_paths, c_nof_input_streams, xstEnable=True, instanceNr=j, nodeNr=tc.nodeFnNrs[i]))
+                                                          
+# Set the treshold register of the statisticsmodules to zero.                                                           
+for k in xrange(tc.nofFnNodes):   
+    for i in range(c_nof_bf_units):
+        print bf[k*c_nof_bf_units+i].st.write_treshold([0])
+
+def gen_data_and_hex_files_bf_ss_wide(gen_hex=True):        
+    # Apply simple SS wide scheme to select e.g. nof_beams_per_subband=4 sets of equal subbands per bf_unit.
+    # . The nof_beams_per_subband must be <= c_nof_subbands=24, because that is the maximum number of different subbands that is available
+    # . In this simple scheme the nof_beams_per_subband needs to be a divider of c_nof_weights=256, so a power of 2
+    # . The settings for only 1 bf_unit are returned. 
+    nof_beams_per_subband = 4
+    select_buf = []  
+    for h in range(c_nof_bf_units):
+        for i in range(c_nof_sp_per_input_stream):  # iterates over the number of single ss units
+            select_buf_line = []
+            for j in range(nof_beams_per_subband):
+                for k in range(c_nof_weights/nof_beams_per_subband): 
+                    select_buf_line.append(i*c_nof_subbands + j) 
+            if (gen_hex == True): 
+                filename = "../../src/hex/ss_wide_" + str(h) + "_" + str(i) + ".hex"
+                mem_init_file.list_to_hex(list_in=select_buf_line, filename=filename, mem_width=ceil_log2(c_nof_subbands_per_stream), mem_depth=c_nof_weights)
+            if (h==0):
+                select_buf.append(select_buf_line)
+    return select_buf    
+
+def gen_data_and_hex_files_bf_weights(gen_hex=True, sel='noise', ampl=1.0):    
+    weightsBfUnit=[]
+    ampl = ampl * 1.0 # Force to float
+    for i in range(c_nof_signal_paths):
+        singleList_real   = dsp_test_weights.create_waveform(sel, ampl, seed=2*i, noiseLevel=0, length=c_nof_weights)
+        singleList_imag   = dsp_test_weights.create_waveform(sel, ampl, seed=2*i+1, noiseLevel=0, length=c_nof_weights)
+        singleList_real   = dsp_test_weights.quantize_waveform(singleList_real)
+        singleList_imag   = dsp_test_weights.quantize_waveform(singleList_imag)
+        if c_debug_print and i==0:
+            print "singleList_real = %s" % singleList_real
+        weightsSignalPath = dsp_test_weights.concatenate_two_lists(singleList_real, singleList_imag, c_in_weight_w)
+        if (gen_hex == True):
+            filename = "../../src/hex/weights_" + str(i) + ".hex"
+            mem_init_file.list_to_hex(list_in=weightsSignalPath, filename=filename, mem_width=2*c_in_weight_w, mem_depth=c_nof_weights)
+        weightsBfUnit.append(weightsSignalPath)
+    return weightsBfUnit    
+
+
+if __name__ == "__main__":      
+  
+  n=0
+  for rep in xrange(tc.repeat):
+      
+      tc.append_log(3, '>>> Rep %d' % rep)
+  
+      ################################################################################
+      ##
+      ## Create settings for ss_wide in bf_unit
+      ##
+      ################################################################################
+      select_buf = gen_data_and_hex_files_bf_ss_wide(c_gen_hex_files) 
+  
+      ################################################################################
+      ##
+      ## Initialize the blockgenerators
+      ##
+      ################################################################################
+      # - Write settings to the block generator 
+      tc.append_log(3, '>>>')
+      tc.append_log(3, '>>> Write settings to the block generator')
+      tc.append_log(3, '>>>')
+      bg.write_block_gen_settings(c_samples_per_packet, c_blocks_per_sync, c_gapsize, c_mem_low_addr, c_mem_high_addr, c_bsn_init)
+      
+      # - Create a list with the input data and write it to the RAMs of the block generator
+      tc.append_log(3, '>>>')
+      tc.append_log(3, '>>> Write data to the waveform RAM of all channels')
+      tc.append_log(3, '>>>')
+  
+      inputData = []
+      for i in xrange(c_nof_input_streams):
+          dataList = bg.generate_data_list(c_nof_sp_per_input_stream, c_nof_subbands, 2048*i*4, i, c_in_dat_w)
+          print dataList
+          print ""
+          bg.write_waveform_ram(dataList, i)
+          dataListComplex = bg.convert_concatenated_to_complex(dataList, c_in_dat_w)
+          inputData.append(dataListComplex)
+          print dataListComplex
+      ################################################################################
+      ##
+      ## Create and Write the weight factors 
+      ##
+      ################################################################################
+
+      tc.append_log(3, '>>>')
+      tc.append_log(3, '>>> Create and write weightfactors for all signal paths on all bf_units ')
+      tc.append_log(3, '>>>')
+     
+      weightsNodes = []
+      for k in xrange(tc.nofFnNodes):                    
+          weightsBf = []
+          for i in range(c_nof_bf_units):
+              weightsBfUnit=[]
+              for j in range(c_nof_signal_paths):
+                  weightsSignalPath = bf[k*c_nof_bf_units+i].generate_weights(c_nof_weights, i+j, i, c_in_weight_w)
+                  bf[k*c_nof_bf_units+i].write_weights(weightsSignalPath, j) 
+                  weightsSignalPathComplex = bg.convert_concatenated_to_complex(weightsSignalPath, c_in_weight_w)
+                  weightsBfUnit.append(weightsSignalPathComplex)
+              weightsBf.append(weightsBfUnit)
+          weightsNodes.append(weightsBf)
+      
+      ################################################################################
+      ##
+      ## Create and Write the selection buffers
+      ##
+      ################################################################################
+      for i in range(tc.nofFnNodes):
+          for j in xrange(c_nof_bf_units):
+              for k in range(c_nof_input_streams):
+                  bf[i*c_nof_bf_units + j].ss_wide[k].write_selects(flatten(select_buf)); 
+  
+      # - Enable the block generator
+      tc.append_log(3, '>>>')
+      tc.append_log(3, '>>> Enable the block generator')
+      tc.append_log(3, '>>>')
+      tc.append_log(3, '')
+      bg.write_enable()
+      
+      ################################################################################
+      ##
+      ## Calculate the reference values
+      ##
+      ################################################################################
+      statisticsAccumulatedNode = []
+      for k in xrange(tc.nofFnNodes):   
+          statisticsAccumulated = []                 
+          for i in range(c_nof_bf_units):
+              statisticsAccumulated.append(bf[k*c_nof_bf_units+i].calculate_beamlets(inputData, select_buf, weightsNodes[k][i], c_in_weight_w, c_blocks_per_sync))
+          statisticsAccumulatedNode.append(statisticsAccumulated)
+  
+      ################################################################################
+      ##
+      ## Read out the beamlet statistics 
+      ##
+      ################################################################################
+      # Wait a while before reading out the statistics
+      if tc.sim == True: 
+          current_time = io.simIO.getSimTime()
+          wait_time = current_time[0] + 2*c_blocks_per_sync * c_nof_weights * c_clk_period
+          do_until_gt(io.simIO.getSimTime, wait_time, s_timeout=3600)
+      else:
+          tc.sleep(1)
+          
+      tc.append_log(3, '>>>')
+      tc.append_log(2, '>>> Rep = %d, n = %d: Read the Beamlet Statistics of all bf_units' % (rep, n))
+      tc.append_log(3, '>>>')
+      tc.append_log(3, '')
+      
+      for k in xrange(tc.nofFnNodes):   
+          beamlet_stats = []
+          for i in range(c_nof_bf_units):
+              beamlet_stats_bf_unit = bf[k*c_nof_bf_units+i].st.read_and_verify_stats(statisticsAccumulatedNode[k][i])
+              beamlet_stats.append(beamlet_stats_bf_unit)
+          
+      # - Disable the block generator
+      tc.append_log(3, '>>>')
+      tc.append_log(3, '>>> Disable the block generator')
+      tc.append_log(3, '>>>')
+      tc.append_log(3, '')
+      bg.write_disable()
+          
+      n+=1
+  
+      
+  ###############################################################################
+  # End
+  tc.set_section_id('')
+  tc.append_log(3, '')
+  tc.append_log(3, '>>>')
+  tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+  tc.append_log(3, '>>>')
+  
+  sys.exit(tc.get_result())
\ No newline at end of file

libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for fn_bf
+--          The DUT can be targeted at unb 0, fn 3 with the same Python scripts 
+--          that are used on hardware. 
+
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, bf_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE bf_lib.bf_pkg.ALL;
+
+ENTITY tb_unb1_fn_bf IS
+GENERIC(
+  --   TYPE t_c_bf IS RECORD
+  --    nof_signal_paths  : POSITIVE; -- = 64
+  --    nof_input_streams : POSITIVE; -- = 16 
+  --    nof_subbands      : POSITIVE; -- = 24
+  --    nof_weights       : POSITIVE; -- = 256
+  --    nof_bf_units      : POSITIVE; -- = 4
+  --    in_dat_w          : POSITIVE; -- = 16
+  --    in_weight_w       : POSITIVE; -- = 16
+  --    bst_gain_w        : INTEGER;  -- = 1
+  --    bst_dat_w         : POSITIVE; -- = 16                                
+  --    out_gain_w        : INTEGER;  -- = -5
+  --    out_dat_w         : POSITIVE; -- = 8
+  --    stat_data_w       : POSITIVE; -- = 56
+  --    stat_data_sz      : POSITIVE; -- = 2
+  --  END RECORD;
+  g_bf : t_c_bf := (64, 16, 24, 256, 4, 16, 16, 1, 16, -5, 8, 56, 2)
+);
+END tb_unb1_fn_bf;
+
+ARCHITECTURE tb OF tb_unb1_fn_bf IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 3; -- Front node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb1_board_fw_version := (1, 0);
+
+  CONSTANT c_cable_delay     : TIME := 12 ns;
+  CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
+  CONSTANT c_clk_period      : TIME := 1 ns; 
+  CONSTANT c_pps_period      : NATURAL := 1000; 
+
+  -- DUT
+  SIGNAL clk                 : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC;
+  SIGNAL eth_rxp             : STD_LOGIC;
+  
+  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version; 
+  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)      := c_id;
+  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+
+  -- Model I2C sensor slaves as on the UniBoard
+  CONSTANT c_fpga_temp_address   : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000";  -- MAX1618 address LOW LOW
+  CONSTANT c_fpga_temp           : INTEGER := 60;
+  CONSTANT c_eth_temp_address    : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001";  -- MAX1618 address MID LOW
+  CONSTANT c_eth_temp            : INTEGER := 40;
+  CONSTANT c_hot_swap_address    : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100";  -- LTC4260 address L L L
+  CONSTANT c_hot_swap_R_sense    : REAL := 0.01;                               -- = 10 mOhm on UniBoard
+  
+  CONSTANT c_uniboard_current    : REAL := 5.0;   -- = assume 5.0 A on UniBoard
+  CONSTANT c_uniboard_supply     : REAL := 48.0;  -- = assume 48.0 V on UniBoard
+  CONSTANT c_uniboard_adin       : REAL := -1.0;  -- = NC on UniBoard
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
+  
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+
+  ------------------------------------------------------------------------------
+  -- 1GbE Loopback model
+  ------------------------------------------------------------------------------  
+  eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+  
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_dut : ENTITY work.unb1_fn_bf
+    GENERIC MAP (
+      g_sim         => c_sim,
+      g_sim_unb_nr  => c_unb_nr,
+      g_sim_node_nr => c_node_nr,
+      g_bf          => g_bf
+    )
+    PORT MAP (
+      -- GENERAL
+      CLK         => clk,
+      PPS         => pps,
+      WDI         => WDI,
+      INTA        => INTA,
+      INTB        => INTB,
+
+      sens_sc     => sens_scl,
+      sens_sd     => sens_sda,
+
+      -- Others
+      VERSION     => VERSION,
+      ID          => ID,
+      TESTIO      => TESTIO,
+
+      -- 1GbE Control Interface
+      ETH_clk     => eth_clk,
+      ETH_SGIN    => eth_rxp,
+      ETH_SGOUT   => eth_txp
+    );
+  
+END tb;