diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..4bb1c670e0143f3de7a3bbb2ec58e05cf6113519
--- /dev/null
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
@@ -0,0 +1,35 @@
+hdl_lib_name = unb1_fn_bf
+hdl_library_clause_name = unb1_fn_bf_lib
+hdl_lib_uses_synth = common technology mm i2c unb1_board bf
+hdl_lib_uses_sim =
+
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_top_level_entity =
+
+synth_files =
+ $HDL_BUILD_DIR/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
+ src/vhdl/mmm_unb1_fn_bf.vhd
+ src/vhdl/node_unb1_fn_bf.vhd
+ src/vhdl/unb1_fn_bf.vhd
+
+test_bench_files =
+ tb/vhdl/tb_unb1_fn_bf.vhd
+
+modelsim_copy_files = src/hex hex
+
+quartus_copy_files = quartus/sopc_unb1_fn_bf.sopc .
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+ ../../libraries/dsp/bf/src/tcl/bf_constraints.tcl
+ quartus/unb1_fn_bf_pins.tcl
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
+
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/quartus/sopc_unb1_fn_bf.sopc b/libraries/dsp/bf/designs/unb1_fn_bf/quartus/sopc_unb1_fn_bf.sopc
new file mode 100644
index 0000000000000000000000000000000000000000..db9f51a8545c8bd1295f5a5e534c36151e9765c5
--- /dev/null
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/quartus/sopc_unb1_fn_bf.sopc
@@ -0,0 +1,1196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="sopc_unb1_fn_bf">
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element altpll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "464";
+ type = "long";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ }
+ element altpll_0.c0
+ {
+ datum _clockDomain
+ {
+ value = "mm_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c1
+ {
+ datum _clockDomain
+ {
+ value = "cal_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c2
+ {
+ datum _clockDomain
+ {
+ value = "tse_clk";
+ type = "String";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=D:\\svnroot\\UniBoard_FP7\\UniBoard\\trunk\\Firmware\\designs\\fn_bf\\build\\synth\\quartus}";
+ type = "String";
+ }
+ }
+ element cpu_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "long";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element ram_ss_ss_wide.mem
+ {
+ datum baseAddress
+ {
+ value = "524288";
+ type = "long";
+ }
+ }
+ element reg_diag_bg.mem
+ {
+ datum baseAddress
+ {
+ value = "352";
+ type = "long";
+ }
+ }
+ element reg_st_sst.mem
+ {
+ datum baseAddress
+ {
+ value = "192";
+ type = "long";
+ }
+ }
+ element ram_st_sst.mem
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "long";
+ }
+ }
+ element ram_bf_weights.mem
+ {
+ datum baseAddress
+ {
+ value = "262144";
+ type = "long";
+ }
+ }
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "472";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "long";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "0";
+ type = "long";
+ }
+ }
+ element ram_dp_ram_from_mm.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "long";
+ }
+ }
+ element reg_dp_ram_from_mm.mem
+ {
+ datum baseAddress
+ {
+ value = "480";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "long";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "384";
+ type = "long";
+ }
+ }
+ element ram_diag_bg.mem
+ {
+ datum baseAddress
+ {
+ value = "32768";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "65536";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "8192";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element pio_debug_wave
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ }
+ element pio_system_info
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element altpll_0.pll_slave
+ {
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "416";
+ type = "long";
+ }
+ }
+ element ram_bf_weights
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ }
+ element ram_diag_bg
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ }
+ element ram_dp_ram_from_mm
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ }
+ element ram_ss_ss_wide
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ }
+ element ram_st_sst
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element reg_diag_bg
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ }
+ element reg_dp_ram_from_mm
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ }
+ element reg_st_sst
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "long";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "320";
+ type = "long";
+ }
+ }
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "432";
+ type = "long";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "448";
+ type = "long";
+ }
+ }
+ element sopc_unb1_fn_bf
+ {
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4SGX230KF40C2" />
+ <parameter name="deviceFamily" value="STRATIXIV" />
+ <parameter name="deviceSpeedGrade" value="" />
+ <parameter name="fabricMode" value="SOPC" />
+ <parameter name="generateLegacySim" value="true" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="true" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="unb1_fn_bf.qpf" />
+ <parameter name="sopcBorderPoints" value="true" />
+ <parameter name="systemHash" value="-61772755527" />
+ <parameter name="timeStamp" value="1423150120590" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module kind="altera_nios2" version="11.1" enabled="1" name="cpu_0">
+ <parameter name="userDefinedSettings" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_perfCounterWidth" value="_32" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bhtPtrSz" value="_8" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="muldiv_multiplierType" value="NoneSmall" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_minInstRegionSize" value="_12" />
+ <parameter name="mpu_minDataRegionSize" value="_12" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mmu_uitlbNumEntries" value="_4" />
+ <parameter name="mmu_udtlbNumEntries" value="_6" />
+ <parameter name="mmu_tlbPtrSz" value="_7" />
+ <parameter name="mmu_tlbNumWays" value="_16" />
+ <parameter name="mmu_processIDNumBits" value="_8" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_TLBMissExcSlave" value="" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="manuallyAssignCpuID" value="false" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="impl" value="Small" />
+ <parameter name="icache_size" value="_4096" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_numTCIM" value="_0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="deviceFamilyName" value="Stratix IV" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="dcache_size" value="_2048" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="dcache_numTCDM" value="_0" />
+ <parameter name="dcache_lineSize" value="_32" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='ram_dp_ram_from_mm.mem' start='0x80' end='0xC0' /><slave name='reg_st_sst.mem' start='0xC0' end='0x100' /><slave name='avs_eth_0.mms_reg' start='0x100' end='0x140' /><slave name='timer_0.s1' start='0x140' end='0x160' /><slave name='reg_diag_bg.mem' start='0x160' end='0x180' /><slave name='reg_unb_sens.mem' start='0x180' end='0x1A0' /><slave name='altpll_0.pll_slave' start='0x1A0' end='0x1B0' /><slave name='pio_debug_wave.s1' start='0x1B0' end='0x1C0' /><slave name='pio_wdi.s1' start='0x1C0' end='0x1D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1D0' end='0x1D8' /><slave name='pio_pps.mem' start='0x1D8' end='0x1E0' /><slave name='reg_dp_ram_from_mm.mem' start='0x1E0' end='0x1E8' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_st_sst.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x80000' /><slave name='ram_ss_ss_wide.mem' start='0x80000' end='0xC0000' /></address-map>]]></parameter>
+ <parameter name="dataAddrWidth" value="20" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="clockFrequency" value="125000000" />
+ <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+ <parameter name="breakOffset" value="32" />
+ </module>
+ <module
+ kind="altera_avalon_onchip_memory2"
+ version="11.1"
+ enabled="1"
+ name="onchip_memory2_0">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName" value="onchip_memory2_0" />
+ <parameter name="blockType" value="M144K" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Stratix IV" />
+ <parameter name="dualPort" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="false" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ kind="altera_avalon_jtag_uart"
+ version="11.1"
+ enabled="1"
+ name="jtag_uart_0">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module kind="altpll" version="11.1" enabled="1" name="altpll_0">
+ <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+ <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix IV" />
+ <parameter name="WIDTH_CLOCK" value="10" />
+ <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ <parameter name="PRIMARY_CLOCK" value="" />
+ <parameter name="INCLK0_INPUT_FREQUENCY" value="40000" />
+ <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+ <parameter name="OPERATION_MODE" value="NORMAL" />
+ <parameter name="PLL_TYPE" value="AUTO" />
+ <parameter name="QUALIFY_CONF_DONE" value="" />
+ <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+ <parameter name="SCAN_CHAIN" value="" />
+ <parameter name="GATE_LOCK_SIGNAL" value="" />
+ <parameter name="GATE_LOCK_COUNTER" value="" />
+ <parameter name="LOCK_HIGH" value="" />
+ <parameter name="LOCK_LOW" value="" />
+ <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+ <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+ <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SKIP_VCO" value="" />
+ <parameter name="SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SWITCH_OVER_TYPE" value="" />
+ <parameter name="FEEDBACK_SOURCE" value="" />
+ <parameter name="BANDWIDTH" value="" />
+ <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+ <parameter name="SPREAD_FREQUENCY" value="" />
+ <parameter name="DOWN_SPREAD" value="" />
+ <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+ <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+ <parameter name="CLK0_MULTIPLY_BY" value="5" />
+ <parameter name="CLK1_MULTIPLY_BY" value="8" />
+ <parameter name="CLK2_MULTIPLY_BY" value="5" />
+ <parameter name="CLK3_MULTIPLY_BY" value="" />
+ <parameter name="CLK4_MULTIPLY_BY" value="" />
+ <parameter name="CLK5_MULTIPLY_BY" value="" />
+ <parameter name="CLK6_MULTIPLY_BY" value="" />
+ <parameter name="CLK7_MULTIPLY_BY" value="" />
+ <parameter name="CLK8_MULTIPLY_BY" value="" />
+ <parameter name="CLK9_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+ <parameter name="CLK0_DIVIDE_BY" value="1" />
+ <parameter name="CLK1_DIVIDE_BY" value="5" />
+ <parameter name="CLK2_DIVIDE_BY" value="1" />
+ <parameter name="CLK3_DIVIDE_BY" value="" />
+ <parameter name="CLK4_DIVIDE_BY" value="" />
+ <parameter name="CLK5_DIVIDE_BY" value="" />
+ <parameter name="CLK6_DIVIDE_BY" value="" />
+ <parameter name="CLK7_DIVIDE_BY" value="" />
+ <parameter name="CLK8_DIVIDE_BY" value="" />
+ <parameter name="CLK9_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+ <parameter name="CLK0_PHASE_SHIFT" value="0" />
+ <parameter name="CLK1_PHASE_SHIFT" value="0" />
+ <parameter name="CLK2_PHASE_SHIFT" value="0" />
+ <parameter name="CLK3_PHASE_SHIFT" value="" />
+ <parameter name="CLK4_PHASE_SHIFT" value="" />
+ <parameter name="CLK5_PHASE_SHIFT" value="" />
+ <parameter name="CLK6_PHASE_SHIFT" value="" />
+ <parameter name="CLK7_PHASE_SHIFT" value="" />
+ <parameter name="CLK8_PHASE_SHIFT" value="" />
+ <parameter name="CLK9_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+ <parameter name="CLK0_DUTY_CYCLE" value="50" />
+ <parameter name="CLK1_DUTY_CYCLE" value="50" />
+ <parameter name="CLK2_DUTY_CYCLE" value="50" />
+ <parameter name="CLK3_DUTY_CYCLE" value="" />
+ <parameter name="CLK4_DUTY_CYCLE" value="" />
+ <parameter name="CLK5_DUTY_CYCLE" value="" />
+ <parameter name="CLK6_DUTY_CYCLE" value="" />
+ <parameter name="CLK7_DUTY_CYCLE" value="" />
+ <parameter name="CLK8_DUTY_CYCLE" value="" />
+ <parameter name="CLK9_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+ <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+ <parameter name="PORT_extclkena0" value="" />
+ <parameter name="PORT_extclkena1" value="" />
+ <parameter name="PORT_extclkena2" value="" />
+ <parameter name="PORT_extclkena3" value="" />
+ <parameter name="PORT_extclk0" value="" />
+ <parameter name="PORT_extclk1" value="" />
+ <parameter name="PORT_extclk2" value="" />
+ <parameter name="PORT_extclk3" value="" />
+ <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+ <parameter name="PORT_clk0" value="PORT_USED" />
+ <parameter name="PORT_clk1" value="PORT_USED" />
+ <parameter name="PORT_clk2" value="PORT_USED" />
+ <parameter name="PORT_clk3" value="PORT_UNUSED" />
+ <parameter name="PORT_clk4" value="PORT_UNUSED" />
+ <parameter name="PORT_clk5" value="PORT_UNUSED" />
+ <parameter name="PORT_clk6" value="PORT_UNUSED" />
+ <parameter name="PORT_clk7" value="PORT_UNUSED" />
+ <parameter name="PORT_clk8" value="PORT_UNUSED" />
+ <parameter name="PORT_clk9" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCLKOUT1" value="" />
+ <parameter name="PORT_SCLKOUT0" value="" />
+ <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK0" value="PORT_USED" />
+ <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+ <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+ <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+ <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+ <parameter name="PORT_ENABLE0" value="" />
+ <parameter name="PORT_ENABLE1" value="" />
+ <parameter name="PORT_LOCKED" value="PORT_USED" />
+ <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+ <parameter name="PORT_FBOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+ <parameter name="PORT_VCOOVERRANGE" value="" />
+ <parameter name="PORT_VCOUNDERRANGE" value="" />
+ <parameter name="DPA_MULTIPLY_BY" value="" />
+ <parameter name="DPA_DIVIDE_BY" value="" />
+ <parameter name="DPA_DIVIDER" value="" />
+ <parameter name="VCO_MULTIPLY_BY" value="" />
+ <parameter name="VCO_DIVIDE_BY" value="" />
+ <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+ <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+ <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+ <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+ <parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
+ <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+ <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+ <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 8 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 40000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
+ <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 25.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 125.00000000 PT#OUTPUT_FREQ1 40.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 125.000000 PT#EFF_OUTPUT_FREQ_VALUE1 40.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1256297171721465.mif PT#ACTIVECLK_CHECK 0</parameter>
+ <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+ <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+ <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+ <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+ <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+ <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="25000000" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
+ </module>
+ <module
+ kind="altera_avalon_pio"
+ version="11.1"
+ enabled="1"
+ name="pio_debug_wave">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="125000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="125000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="125000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_bf_weights">
+ <parameter name="g_adr_w" value="16" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_st_sst">
+ <parameter name="g_adr_w" value="12" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg">
+ <parameter name="g_adr_w" value="13" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diag_bg">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_ram_from_mm">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_dp_ram_from_mm">
+ <parameter name="g_adr_w" value="4" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_st_sst">
+ <parameter name="g_adr_w" value="4" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_ss_ss_wide">
+ <parameter name="g_adr_w" value="16" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+ <parameter name="AUTO_MM_CLOCK_RATE" value="125000000" />
+ </module>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01d0" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="altpll_0.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01a0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="jtag_uart_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="altpll_0.inclk_interface" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_debug_wave.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_debug_wave.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01b0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0140" />
+ </connection>
+ <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01c0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="onchip_memory2_0.clk1" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_bf_weights.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_bf_weights.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00040000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_st_sst.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_st_sst.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_diag_bg.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_bg.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x8000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_diag_bg.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_bg.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0160" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0180" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="rom_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01d8" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dp_ram_from_mm.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_ram_from_mm.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01e0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_dp_ram_from_mm.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_dp_ram_from_mm.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_st_sst.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_st_sst.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00c0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_ss_ss_wide.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_ss_ss_wide.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00080000" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00010000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+</system>
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/quartus/unb1_fn_bf_pins.tcl b/libraries/dsp/bf/designs/unb1_fn_bf/quartus/unb1_fn_bf_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..14269479e73f36b1c577213c4d4438c7d8409b05
--- /dev/null
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/quartus/unb1_fn_bf_pins.tcl
@@ -0,0 +1,26 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6d33133cea30cbedc92d58dd960d8670564b89cd
--- /dev/null
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -0,0 +1,469 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, bf_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+USE bf_lib.bf_pkg.ALL;
+
+ENTITY mmm_fn_bf IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_bf : t_c_bf := c_bf
+ );
+ PORT (
+ xo_clk : IN STD_LOGIC;
+ xo_rst_n : IN STD_LOGIC;
+ xo_rst : IN STD_LOGIC;
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : OUT STD_LOGIC;
+ mm_locked : OUT STD_LOGIC;
+
+ pout_wdi : OUT STD_LOGIC;
+
+ -- Manual WDI override
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso;
+
+ -- system_info
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso;
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso;
+
+ -- Diagnostics
+ reg_diagnostics_mosi : OUT t_mem_mosi;
+ reg_diagnostics_miso : IN t_mem_miso;
+
+ -- Beamformer Node
+ -- . block generator
+ reg_diag_bg_mosi : OUT t_mem_mosi;
+ reg_diag_bg_miso : IN t_mem_miso;
+ ram_diag_bg_mosi : OUT t_mem_mosi;
+ ram_diag_bg_miso : IN t_mem_miso;
+ -- . beam former
+ ram_ss_ss_wide_mosi : OUT t_mem_mosi;
+ ram_ss_ss_wide_miso : IN t_mem_miso;
+ ram_bf_weights_mosi : OUT t_mem_mosi;
+ ram_bf_weights_miso : IN t_mem_miso;
+ ram_st_sst_bf_mosi : OUT t_mem_mosi;
+ ram_st_sst_bf_miso : IN t_mem_miso;
+ reg_st_sst_bf_mosi : OUT t_mem_mosi;
+ reg_st_sst_bf_miso : IN t_mem_miso;
+
+ -- dp_offload
+ reg_dp_ram_from_mm_mosi : OUT t_mem_mosi;
+ reg_dp_ram_from_mm_miso : IN t_mem_miso;
+ ram_dp_ram_from_mm_mosi : OUT t_mem_mosi;
+ ram_dp_ram_from_mm_miso : IN t_mem_miso;
+ -- . Nof words to offload selection
+ reg_dp_split_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_split_miso : IN t_mem_miso;
+ reg_dp_pkt_merge_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_pkt_merge_miso : IN t_mem_miso;
+
+ -- eth1g
+ eth1g_tse_clk : OUT STD_LOGIC;
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso
+
+ );
+END mmm_fn_bf;
+
+
+ARCHITECTURE str OF mmm_fn_bf IS
+
+ -- Application specific constants (or generics)
+ CONSTANT c_bg_diag_wave_period : NATURAL := 4;
+
+ -- Actual MM address widths, the MM data width is fixed at the default c_word_w=32
+ CONSTANT c_reg_diag_bg_addr_w : NATURAL := 3;
+ CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(c_bg_diag_wave_period) + ceil_log2(g_bf.nof_subbands*g_bf.nof_signal_paths/g_bf.nof_input_streams)+ceil_log2(g_bf.nof_input_streams);
+ CONSTANT c_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_signal_paths*g_bf.nof_weights);
+ CONSTANT c_ram_st_sst_bf_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.stat_data_sz*g_bf.nof_weights*c_nof_complex);
+ CONSTANT c_reg_st_sst_bf_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units)*2; -- 2 bits reserved for single reg_st_sst.
+ CONSTANT c_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_weights*g_bf.nof_signal_paths);
+ -- BF offload
+ CONSTANT c_hdr_nof_words : NATURAL := c_network_total_header_32b_nof_words;
+ CONSTANT c_dp_ram_mm_nof_words : NATURAL := c_hdr_nof_words * (c_eth_data_w/c_word_w);
+ CONSTANT c_dp_ram_mm_adr_w : NATURAL := ceil_log2(c_dp_ram_mm_nof_words);
+
+ -- Simulation
+ CONSTANT c_mm_clk_period : TIME := 100 ps;
+ CONSTANT c_tse_clk_period : TIME := 8 ns;
+
+ CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
+ CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
+
+ SIGNAL i_mm_clk : STD_LOGIC := '1';
+ SIGNAL i_tse_clk : STD_LOGIC := '1';
+
+ ----------------------------------------------------------------------------
+ -- mm_file component
+ ----------------------------------------------------------------------------
+ COMPONENT mm_file
+ GENERIC(
+ g_file_prefix : STRING;
+ g_mm_clk_period : TIME := c_mm_clk_period;
+ g_update_on_change : BOOLEAN := FALSE;
+ g_mm_rd_latency : NATURAL := 1
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi;
+ mm_master_in : IN t_mem_miso
+ );
+ END COMPONENT;
+
+ CONSTANT c_dut_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"002286080001";
+ SIGNAL eth_psc_access : STD_LOGIC;
+
+
+ SIGNAL reg_ppsh_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_ppsh_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth1g_reg_miso : t_mem_miso;
+
+ SIGNAL eth1g_reg_proc_mosi : t_mem_mosi;
+ SIGNAL eth1g_reg_proc_miso : t_mem_miso;
+
+ CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
+ CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
+
+ SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
+ SIGNAL sim_eth_psc_access : STD_LOGIC;
+
+ SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
+
+BEGIN
+
+ mm_clk <= i_mm_clk;
+ eth1g_tse_clk <= i_tse_clk;
+
+ ----------------------------------------------------------------------------
+ -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ ----------------------------------------------------------------------------
+ gen_mm_file_io : IF g_sim = TRUE GENERATE
+
+ i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
+ mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
+
+ i_tse_clk <= NOT i_tse_clk AFTER c_tse_clk_period/2;
+ eth1g_mm_rst <= '1', '0' AFTER c_tse_clk_period*5;
+
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_diagnostics : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
+ PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+
+ u_mm_file_reg_dp_ram_from_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_RAM_FROM_MM")
+ PORT MAP(mm_rst, i_mm_clk, reg_dp_ram_from_mm_mosi, reg_dp_ram_from_mm_miso );
+
+ u_mm_file_ram_dp_ram_from_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_FROM_MM")
+ PORT MAP(mm_rst, i_mm_clk, ram_dp_ram_from_mm_mosi, ram_dp_ram_from_mm_miso );
+
+-- u_mm_file_ram_dp_ram_to_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_TO_MM")
+-- PORT MAP(mm_rst, i_mm_clk, ram_dp_ram_to_mm_mosi, ram_dp_ram_to_mm_miso );
+
+ u_mm_file_reg_dp_split : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SPLIT")
+ PORT MAP(mm_rst, i_mm_clk, reg_dp_split_mosi, reg_dp_split_miso );
+
+ u_mm_file_reg_dp_pkt_merge : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_PKT_MERGE")
+ PORT MAP(mm_rst, i_mm_clk, reg_dp_pkt_merge_mosi, reg_dp_pkt_merge_miso );
+
+ u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_ram_bf_weights : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+ PORT MAP(mm_rst, i_mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+
+ u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ PORT MAP(mm_rst, i_mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+
+ u_mm_file_ram_st_sst_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ PORT MAP(mm_rst, i_mm_clk, ram_st_sst_bf_mosi, ram_st_sst_bf_miso );
+
+ u_mm_file_reg_st_sst_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ST_SST")
+ PORT MAP(mm_rst, i_mm_clk, reg_st_sst_bf_mosi, reg_st_sst_bf_miso );
+
+ u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
+
+ u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
+
+
+ ----------------------------------------------------------------------------
+ -- 1GbE setup sequence normally performed by unb_os@NIOS
+ ----------------------------------------------------------------------------
+ p_eth_setup : PROCESS
+ BEGIN
+ sim_eth_mm_bus_switch <= '1';
+
+ eth1g_tse_mosi.wr <= '0';
+ eth1g_tse_mosi.rd <= '0';
+ WAIT FOR 400 ns;
+ WAIT UNTIL rising_edge(i_mm_clk);
+ proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+
+ -- Enable RX
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ sim_eth_mm_bus_switch <= '0';
+
+ WAIT;
+ END PROCESS;
+
+ p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
+ BEGIN
+ IF sim_eth_mm_bus_switch = '1' THEN
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ ELSE
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ END IF;
+ END PROCESS;
+
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- SOPC system
+ -----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- SOPC for synthesis
+ ----------------------------------------------------------------------------
+ gen_sopc : IF g_sim = FALSE GENERATE
+
+ u_sopc : ENTITY work.sopc_unb1_fn_bf
+ PORT MAP (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs2_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_unb_sens
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_st_sst
+ coe_address_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.address(c_ram_st_sst_bf_addr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_ram_st_sst => OPEN,
+ coe_read_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.rd,
+ coe_readdata_export_to_the_ram_st_sst => ram_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_ram_st_sst => OPEN,
+ coe_write_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wr,
+ coe_writedata_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_st_sst
+ coe_address_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.address(c_reg_st_sst_bf_addr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_reg_st_sst => OPEN,
+ coe_read_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.rd,
+ coe_readdata_export_to_the_reg_st_sst => reg_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_st_sst => OPEN,
+ coe_write_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wr,
+ coe_writedata_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_ss_ss_wide
+ coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.address(c_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.rd,
+ coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wr,
+ coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_bf_weights
+ coe_address_export_from_the_ram_bf_weights => ram_bf_weights_mosi.address(c_ram_bf_weights_addr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_ram_bf_weights => OPEN,
+ coe_read_export_from_the_ram_bf_weights => ram_bf_weights_mosi.rd,
+ coe_readdata_export_to_the_ram_bf_weights => ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_ram_bf_weights => OPEN,
+ coe_write_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wr,
+ coe_writedata_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_bg_diag_bg
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_addr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_diag_bg
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_dp_ram_from_mm
+ coe_clk_export_from_the_reg_dp_ram_from_mm => OPEN,
+ coe_reset_export_from_the_reg_dp_ram_from_mm => OPEN,
+ coe_address_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.address(0),
+ coe_read_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_dp_ram_from_mm
+ coe_clk_export_from_the_ram_dp_ram_from_mm => OPEN,
+ coe_reset_export_from_the_ram_dp_ram_from_mm => OPEN,
+ coe_address_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.address(c_dp_ram_mm_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.rd,
+ coe_readdata_export_to_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wr,
+ coe_writedata_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+ END GENERATE;
+END;
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..983302f31137681a045c4e42feca6a26d6c05b1c
--- /dev/null
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
@@ -0,0 +1,219 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, diag_lib, eth_lib, tech_tse_lib, bf_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+USE bf_lib.ALL;
+USE bf_lib.bf_pkg.ALL;
+
+ENTITY node_unb1_fn_bf IS
+ GENERIC(
+ g_use_bf : BOOLEAN := TRUE; -- FALSE skips instantiation of the BF
+ g_bf : t_c_bf := c_bf;
+ g_bf_weights_file_name : STRING := "../../../../../dsp/bf/build/data/weights"; -- default file location for synthesis
+ g_ss_wide_file_prefix : STRING := "UNUSED"; -- path_to_file
+ g_bf_offload : BOOLEAN := FALSE; -- Use DP TX offload to stream BF output towards LCU
+ g_use_block_gen : BOOLEAN := TRUE; -- FALSE uses external input.
+ g_block_gen_file_prefix : STRING := "../../../../../modules/Lofar/diag/src/data/bf_in_data"; -- default file location for synthesis
+ g_bg_diag_wave_period : POSITIVE := 4; -- This generic defines the period of the waveform that is generated with the block generator.
+ g_weights_write_only : BOOLEAN := FALSE -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+ );
+ PORT(
+ -- System
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC; -- 125 MHz from xo_clk PLL in SOPC system
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC; -- 200 MHz from CLK system clock
+ -- MM interface
+ -- . block generator
+ reg_diag_bg_mosi : IN t_mem_mosi;
+ reg_diag_bg_miso : OUT t_mem_miso;
+ ram_diag_bg_mosi : IN t_mem_mosi;
+ ram_diag_bg_miso : OUT t_mem_miso;
+ -- . beam former
+ ram_ss_ss_wide_mosi : IN t_mem_mosi;
+ ram_ss_ss_wide_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_bf_weights_mosi : IN t_mem_mosi;
+ ram_bf_weights_miso : OUT t_mem_miso;
+ ram_st_sst_bf_mosi : IN t_mem_mosi;
+ ram_st_sst_bf_miso : OUT t_mem_miso;
+ reg_st_sst_bf_mosi : IN t_mem_mosi;
+ reg_st_sst_bf_miso : OUT t_mem_miso;
+ -- . hdr_insert and hdr_remove for bf_out_offload
+ reg_hdr_insert_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_hdr_insert_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ -- . Nof words to offload selection
+ reg_dp_split_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_split_miso : OUT t_mem_miso;
+ reg_dp_pkt_merge_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_pkt_merge_miso : OUT t_mem_miso;
+
+ -- ST interface, BF subbands in
+ ext_in_sosi_arr : IN t_dp_sosi_arr( g_bf.nof_input_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ ext_in_siso_arr : OUT t_dp_siso_arr( g_bf.nof_input_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rst);
+
+ -- ST interface, BF beamlets out
+ out_raw_sosi_arr : OUT t_dp_sosi_arr( g_bf.nof_bf_units-1 DOWNTO 0); -- raw beamlets
+ out_bst_sosi_arr : OUT t_dp_sosi_arr( g_bf.nof_bf_units-1 DOWNTO 0); -- 16b beamlets; a selection can be offloaded via bf_out_offload_tx_sosi_arr.
+ out_qua_sosi_arr : OUT t_dp_sosi_arr( g_bf.nof_bf_units-1 DOWNTO 0); -- 8b beamlets
+
+ -- DP offload for 1GbE
+ bf_out_offload_tx_sosi_arr : OUT t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0); -- 16b beamlets
+ bf_out_offload_tx_siso_arr : IN t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst)
+ );
+END node_unb1_fn_bf;
+
+ARCHITECTURE str OF node_unb1_fn_bf IS
+
+ CONSTANT c_buf_addr_w : NATURAL := ceil_log2(g_bg_diag_wave_period) + ceil_log2(g_bf.nof_subbands*g_bf.nof_signal_paths/g_bf.nof_input_streams);
+
+ SIGNAL bf_in_sosi_arr : t_dp_sosi_arr( g_bf.nof_input_streams-1 DOWNTO 0);
+ SIGNAL bg_out_sosi_arr : t_dp_sosi_arr( g_bf.nof_input_streams-1 DOWNTO 0);
+
+ SIGNAL i_out_bst_sosi_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
+
+BEGIN
+
+ out_bst_sosi_arr <= i_out_bst_sosi_arr;
+
+ ---------------------------------------------------------------------------------------
+ -- Use Block Generator input by default
+ ---------------------------------------------------------------------------------------
+ gen_block_gen : IF g_use_block_gen = TRUE GENERATE
+ u_bg : ENTITY diag_lib.mms_diag_block_gen
+ GENERIC MAP(
+ g_blk_sync => TRUE,
+ g_nof_output_streams => g_bf.nof_input_streams,
+ g_buf_dat_w => c_nof_complex*g_bf.in_dat_w,
+ g_buf_addr_w => c_buf_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_name_prefix => g_block_gen_file_prefix
+ )
+ PORT MAP(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_sosi_arr => bg_out_sosi_arr
+ );
+
+ bf_in_sosi_arr <= bg_out_sosi_arr;
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- Override Block Generator output and use external input instead
+ ---------------------------------------------------------------------------------------
+ gen_ext_in : IF g_use_block_gen = FALSE GENERATE
+ bf_in_sosi_arr <= ext_in_sosi_arr;
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- Beam Former
+ ---------------------------------------------------------------------------------------
+ gen_bf : IF g_use_bf = TRUE GENERATE
+ u_bf : ENTITY bf_lib.bf
+ GENERIC MAP (
+ g_bf => g_bf,
+ g_bf_weights_file_name => g_bf_weights_file_name,
+ g_ss_wide_file_prefix => g_ss_wide_file_prefix,
+ g_weights_write_only => g_weights_write_only
+ )
+ PORT MAP (
+ -- System
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM interface
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ ram_st_sst_mosi => ram_st_sst_bf_mosi,
+ ram_st_sst_miso => ram_st_sst_bf_miso,
+ reg_st_sst_mosi => reg_st_sst_bf_mosi,
+ reg_st_sst_miso => reg_st_sst_bf_miso,
+
+ -- ST interface
+ in_sosi_arr => bf_in_sosi_arr,
+ in_siso_arr => ext_in_siso_arr,
+
+ out_raw_sosi_arr => out_raw_sosi_arr, -- raw beamlets
+ out_bst_sosi_arr => i_out_bst_sosi_arr, -- 16b beamlets
+ out_qua_sosi_arr => out_qua_sosi_arr -- 8b beamlets
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- Offload 16b beamlets from out_bst_sosi_arr to udp_offload TX port in ctrl_unb_common
+ ---------------------------------------------------------------------------------------
+ gen_bf_offload : IF g_bf_offload = TRUE GENERATE
+ u_dp_offload : ENTITY dp_lib.dp_offload_tx
+ GENERIC MAP (
+ g_nof_streams => g_bf.nof_bf_units,
+ g_data_w => c_eth_data_w,
+ g_block_size => g_bf.nof_weights, -- = 256
+ g_block_nof_sel_words => 20,
+ g_nof_words_per_pkt => 360,
+ g_hdr_nof_words => c_network_total_header_32b_nof_words,
+ g_use_complex => TRUE,
+ g_use_input_fifo => TRUE,
+ g_use_output_fifo => TRUE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ reg_hdr_insert_mosi => reg_hdr_insert_mosi,
+ ram_hdr_insert_mosi => ram_hdr_insert_mosi,
+ reg_dp_split_mosi => reg_dp_split_mosi,
+ reg_dp_split_miso => reg_dp_split_miso,
+ reg_dp_pkt_merge_mosi => reg_dp_pkt_merge_mosi,
+ reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso,
+
+ dp_sosi_arr => i_out_bst_sosi_arr,
+ dp_siso_arr => OPEN, -- No flow control, so we're instantiating an input FIFO.
+
+ tx_sosi_arr => bf_out_offload_tx_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0),
+ tx_siso_arr => bf_out_offload_tx_siso_arr(g_bf.nof_bf_units-1 DOWNTO 0)
+ );
+ END GENERATE;
+
+END str;
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5a9dcedc5f11a2951d2a814d0bc287d809cda9b7
--- /dev/null
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
@@ -0,0 +1,414 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, bf_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+USE bf_lib.bf_pkg.ALL;
+
+ENTITY unb1_fn_bf IS
+ GENERIC (
+ g_design_name : STRING := "unb1_fn_bf";
+ g_design_note : STRING := "UNUSED";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
+ g_bf : t_c_bf := c_bf
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC
+ );
+END unb1_fn_bf;
+
+
+ARCHITECTURE str OF unb1_fn_bf IS
+
+
+ CONSTANT c_bf_offload : BOOLEAN := FALSE; -- Offload BF out(0) datapath to 1GbE UDP TX port
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 0, 0, 0, 1);
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (2, 3); -- firmware version x.y
+ CONSTANT c_nof_streams : NATURAL := c_eth_nof_udp_ports;
+ CONSTANT c_weights_write_only : BOOLEAN := TRUE; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+
+ -- Use default RAM inti files. The RAM init file for simulation lies one ../ level further way then for synthesis
+ CONSTANT c_bf_weights_file_name : STRING := "UNUSED";
+ CONSTANT c_ss_wide_file_prefix : STRING := "hex/ss_wide";
+ CONSTANT c_block_gen_file_prefix : STRING := "UNUSED";
+
+ -- BF offload
+ CONSTANT c_hdr_nof_words : NATURAL := c_network_total_header_32b_nof_words;
+ CONSTANT c_dp_ram_mm_nof_words : NATURAL := c_hdr_nof_words * (c_eth_data_w/c_word_w);
+ CONSTANT c_dp_ram_mm_adr_w : NATURAL := ceil_log2(c_dp_ram_mm_nof_words);
+
+ -- System
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL dp_pps : STD_LOGIC;
+
+ SIGNAL app_led_red : STD_LOGIC := '0';
+ SIGNAL app_led_green : STD_LOGIC := '1';
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+
+ -- PPSH
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+ SIGNAL eth1g_led : t_tech_tse_led;
+
+ -- eth1g UDP streaming ports
+ SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
+ SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
+
+ -- MM registers and RAM
+ -- . block generator
+ SIGNAL reg_diag_bg_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_diag_bg_miso : t_mem_miso;
+ SIGNAL ram_diag_bg_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_diag_bg_miso : t_mem_miso;
+ -- . beam former
+ SIGNAL ram_bf_weights_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_bf_weights_miso : t_mem_miso;
+ SIGNAL ram_st_sst_bf_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_sst_bf_miso : t_mem_miso;
+ SIGNAL reg_st_sst_bf_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_st_sst_bf_miso : t_mem_miso;
+ SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_ss_ss_wide_miso : t_mem_miso;
+
+ -- . uniboard sensors
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+
+ SIGNAL reg_diagnostics_mosi : t_mem_mosi;
+ SIGNAL reg_diagnostics_miso : t_mem_miso;
+ -- . dp_ram_from_mm for DP offload (header insertion)
+ SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
+ SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL ram_dp_ram_from_mm_mosi : t_mem_mosi;
+ SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL ram_dp_ram_to_mm_mosi : t_mem_mosi;
+ SIGNAL ram_dp_ram_to_mm_miso : t_mem_miso;
+
+ SIGNAL reg_dp_split_mosi : t_mem_mosi;
+ SIGNAL reg_dp_split_miso : t_mem_miso;
+
+ SIGNAL reg_dp_pkt_merge_mosi : t_mem_mosi;
+ SIGNAL reg_dp_pkt_merge_miso : t_mem_miso;
+
+ -- ST interface
+ SIGNAL beams_sosi_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_udp_offload => sel_a_b(c_bf_offload, TRUE, FALSE),
+ g_aux => c_unb1_board_aux,
+ g_udp_offload_nof_streams => c_nof_streams
+ )
+ PORT MAP (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports to offload BF out
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_mmm : ENTITY work.mmm_fn_bf
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_bf => g_bf
+ )
+ PORT MAP(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Diagnostics
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- beamformer
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ ram_st_sst_bf_mosi => ram_st_sst_bf_mosi,
+ ram_st_sst_bf_miso => ram_st_sst_bf_miso,
+ reg_st_sst_bf_mosi => reg_st_sst_bf_mosi,
+ reg_st_sst_bf_miso => reg_st_sst_bf_miso,
+
+ -- dp_offload -- dp_offload
+ reg_dp_ram_from_mm_mosi => reg_dp_ram_from_mm_mosi,
+ reg_dp_ram_from_mm_miso => reg_dp_ram_from_mm_miso,
+ ram_dp_ram_from_mm_mosi => ram_dp_ram_from_mm_mosi,
+ ram_dp_ram_from_mm_miso => ram_dp_ram_from_mm_miso,
+ reg_dp_split_mosi => reg_dp_split_mosi,
+ reg_dp_split_miso => reg_dp_split_miso,
+ reg_dp_pkt_merge_mosi => reg_dp_pkt_merge_mosi,
+ reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso
+ );
+
+ u_node_unb1_fn_bf : ENTITY work.node_unb1_fn_bf
+ GENERIC MAP(
+ g_bf => g_bf,
+ g_bf_offload => c_bf_offload,
+ g_bf_weights_file_name => c_bf_weights_file_name,
+ g_ss_wide_file_prefix => c_ss_wide_file_prefix,
+ g_block_gen_file_prefix => c_block_gen_file_prefix,
+ g_weights_write_only => c_weights_write_only
+ )
+ PORT MAP(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- . beam former
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_st_sst_bf_mosi => ram_st_sst_bf_mosi,
+ ram_st_sst_bf_miso => ram_st_sst_bf_miso,
+ reg_st_sst_bf_mosi => reg_st_sst_bf_mosi,
+ reg_st_sst_bf_miso => reg_st_sst_bf_miso,
+
+ -- . hdr_insert for dp offload
+ reg_hdr_insert_mosi => reg_dp_ram_from_mm_mosi,
+ ram_hdr_insert_mosi => ram_dp_ram_from_mm_mosi,
+
+ -- ST interface
+ out_bst_sosi_arr => OPEN, -- 16b beamlets
+ out_qua_sosi_arr => beams_sosi_arr, -- 8b beamlets
+
+ -- DP offload of 16b beamlets to 1GbE via ctrl_unb_common
+ bf_out_offload_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ bf_out_offload_tx_siso_arr => eth1g_udp_tx_siso_arr
+ );
+END;
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/tb/python/tc_unb1_fn_bf.py b/libraries/dsp/bf/designs/unb1_fn_bf/tb/python/tc_unb1_fn_bf.py
new file mode 100644
index 0000000000000000000000000000000000000000..71c3b0e4218fe45c2a97f0ec77676085ec66aea8
--- /dev/null
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/tb/python/tc_unb1_fn_bf.py
@@ -0,0 +1,292 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2012
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for the fn_bf design
+
+ Usage: python tc_unb1_fn_bf.py --unb 0 --fn 0:3 --rep 1 -n 1 -v 6
+
+"""
+
+###############################################################################
+# System imports
+import sys
+import test_case
+import node_io
+import pi_unb_sens
+import pi_diag_block_gen
+import pi_bf_bf
+import pi_st_sst
+import pi_ss_ss_wide
+import unb_apertif as apr
+from tools import *
+from common import *
+import mem_init_file
+
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+tc.set_result('PASSED')
+tc.append_log(3, '>>>')
+tc.append_log(1, '>>> Title : Test case for the fn_bf design on %s' % tc.unb_nodes_string())
+tc.append_log(3, '>>>')
+tc.append_log(3, '')
+
+# Constants/Generics that are shared between VHDL and Python
+# Name Value Default Description
+# START_VHDL_GENERICS
+c_nof_signal_paths = 16 # 64
+c_nof_input_streams = 4 # 16
+c_nof_subbands = 24 # 24
+c_nof_weights = 256 # 256
+c_nof_bf_units = 4 # 4
+c_in_dat_w = 16 # 16
+c_in_weight_w = 16 # 16
+c_gain_w = -1 # -1
+c_bst_dat_w = 16 # 16
+c_bst_lsb_w = 14 # 14
+c_out_dat_w = 39 # 8 for the correlator, 16 for udp_offload, 39 for capturein databuffer of testbench
+c_out_lsb_w = 14 # 14
+c_stat_data_w = 56 # 56
+c_stat_data_sz = 2 # 2
+c_bf_weights_file_name = "../../../build/data/weights" # -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
+# END_VHDL_GENERICS
+
+c_blocks_per_sync = 100
+c_clk_period = 1 # ns
+# Overrule constant definitions when testcase runs on hardware.
+if tc.sim==False:
+ c_nof_signal_paths = 64
+ c_nof_input_streams = 16
+ c_nof_subbands = 24
+ c_nof_weights = 256
+ c_nof_bf_units = 4
+ c_in_dat_w = 16
+ c_in_weight_w = 16
+ c_gain_w = -1
+ c_bst_dat_w = 16
+ c_bst_lsb_w = 14
+ c_out_dat_w = 39 # 8 for the correlator, 16 for udp_offload, 39 for capturein databuffer of testbench
+ c_out_lsb_w = 14
+ c_stat_data_w = 56
+ c_stat_data_sz = 2
+ c_bf_weights_file_name = "../../../build/data/weights" # -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
+ c_blocks_per_sync = 781250
+
+c_nof_sp_per_input_stream = c_nof_signal_paths / c_nof_input_streams
+c_nof_subbands_per_stream = c_nof_subbands*c_nof_sp_per_input_stream
+
+# Define settings for the block generator
+c_samples_per_packet = c_nof_sp_per_input_stream * c_nof_subbands
+c_gapsize = c_nof_weights - c_samples_per_packet
+c_mem_low_addr = 0
+c_mem_high_addr = c_samples_per_packet-1
+c_bsn_init = 42
+c_gen_hex_files = True
+
+# Create access object for all nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+# Create instances for the block generator (BG)
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, nofChannels=c_nof_input_streams, ramSizePerChannel= 4*2**(ceil_log2(c_samples_per_packet)))
+
+# Create instances for the beamformer units (BF)
+bf=[]
+for i in range(tc.nofFnNodes):
+ for j in xrange(c_nof_bf_units):
+ bf.append(pi_bf_bf.PiBfBf(tc, io, c_nof_weights, c_nof_signal_paths, c_nof_input_streams, xstEnable=True, instanceNr=j, nodeNr=tc.nodeFnNrs[i]))
+
+# Set the treshold register of the statisticsmodules to zero.
+for k in xrange(tc.nofFnNodes):
+ for i in range(c_nof_bf_units):
+ print bf[k*c_nof_bf_units+i].st.write_treshold([0])
+
+def gen_data_and_hex_files_bf_ss_wide(gen_hex=True):
+ # Apply simple SS wide scheme to select e.g. nof_beams_per_subband=4 sets of equal subbands per bf_unit.
+ # . The nof_beams_per_subband must be <= c_nof_subbands=24, because that is the maximum number of different subbands that is available
+ # . In this simple scheme the nof_beams_per_subband needs to be a divider of c_nof_weights=256, so a power of 2
+ # . The settings for only 1 bf_unit are returned.
+ nof_beams_per_subband = 4
+ select_buf = []
+ for h in range(c_nof_bf_units):
+ for i in range(c_nof_sp_per_input_stream): # iterates over the number of single ss units
+ select_buf_line = []
+ for j in range(nof_beams_per_subband):
+ for k in range(c_nof_weights/nof_beams_per_subband):
+ select_buf_line.append(i*c_nof_subbands + j)
+ if (gen_hex == True):
+ filename = "../../src/hex/ss_wide_" + str(h) + "_" + str(i) + ".hex"
+ mem_init_file.list_to_hex(list_in=select_buf_line, filename=filename, mem_width=ceil_log2(c_nof_subbands_per_stream), mem_depth=c_nof_weights)
+ if (h==0):
+ select_buf.append(select_buf_line)
+ return select_buf
+
+def gen_data_and_hex_files_bf_weights(gen_hex=True, sel='noise', ampl=1.0):
+ weightsBfUnit=[]
+ ampl = ampl * 1.0 # Force to float
+ for i in range(c_nof_signal_paths):
+ singleList_real = dsp_test_weights.create_waveform(sel, ampl, seed=2*i, noiseLevel=0, length=c_nof_weights)
+ singleList_imag = dsp_test_weights.create_waveform(sel, ampl, seed=2*i+1, noiseLevel=0, length=c_nof_weights)
+ singleList_real = dsp_test_weights.quantize_waveform(singleList_real)
+ singleList_imag = dsp_test_weights.quantize_waveform(singleList_imag)
+ if c_debug_print and i==0:
+ print "singleList_real = %s" % singleList_real
+ weightsSignalPath = dsp_test_weights.concatenate_two_lists(singleList_real, singleList_imag, c_in_weight_w)
+ if (gen_hex == True):
+ filename = "../../src/hex/weights_" + str(i) + ".hex"
+ mem_init_file.list_to_hex(list_in=weightsSignalPath, filename=filename, mem_width=2*c_in_weight_w, mem_depth=c_nof_weights)
+ weightsBfUnit.append(weightsSignalPath)
+ return weightsBfUnit
+
+
+if __name__ == "__main__":
+
+ n=0
+ for rep in xrange(tc.repeat):
+
+ tc.append_log(3, '>>> Rep %d' % rep)
+
+ ################################################################################
+ ##
+ ## Create settings for ss_wide in bf_unit
+ ##
+ ################################################################################
+ select_buf = gen_data_and_hex_files_bf_ss_wide(c_gen_hex_files)
+
+ ################################################################################
+ ##
+ ## Initialize the blockgenerators
+ ##
+ ################################################################################
+ # - Write settings to the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Write settings to the block generator')
+ tc.append_log(3, '>>>')
+ bg.write_block_gen_settings(c_samples_per_packet, c_blocks_per_sync, c_gapsize, c_mem_low_addr, c_mem_high_addr, c_bsn_init)
+
+ # - Create a list with the input data and write it to the RAMs of the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Write data to the waveform RAM of all channels')
+ tc.append_log(3, '>>>')
+
+ inputData = []
+ for i in xrange(c_nof_input_streams):
+ dataList = bg.generate_data_list(c_nof_sp_per_input_stream, c_nof_subbands, 2048*i*4, i, c_in_dat_w)
+ print dataList
+ print ""
+ bg.write_waveform_ram(dataList, i)
+ dataListComplex = bg.convert_concatenated_to_complex(dataList, c_in_dat_w)
+ inputData.append(dataListComplex)
+ print dataListComplex
+ ################################################################################
+ ##
+ ## Create and Write the weight factors
+ ##
+ ################################################################################
+
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Create and write weightfactors for all signal paths on all bf_units ')
+ tc.append_log(3, '>>>')
+
+ weightsNodes = []
+ for k in xrange(tc.nofFnNodes):
+ weightsBf = []
+ for i in range(c_nof_bf_units):
+ weightsBfUnit=[]
+ for j in range(c_nof_signal_paths):
+ weightsSignalPath = bf[k*c_nof_bf_units+i].generate_weights(c_nof_weights, i+j, i, c_in_weight_w)
+ bf[k*c_nof_bf_units+i].write_weights(weightsSignalPath, j)
+ weightsSignalPathComplex = bg.convert_concatenated_to_complex(weightsSignalPath, c_in_weight_w)
+ weightsBfUnit.append(weightsSignalPathComplex)
+ weightsBf.append(weightsBfUnit)
+ weightsNodes.append(weightsBf)
+
+ ################################################################################
+ ##
+ ## Create and Write the selection buffers
+ ##
+ ################################################################################
+ for i in range(tc.nofFnNodes):
+ for j in xrange(c_nof_bf_units):
+ for k in range(c_nof_input_streams):
+ bf[i*c_nof_bf_units + j].ss_wide[k].write_selects(flatten(select_buf));
+
+ # - Enable the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Enable the block generator')
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '')
+ bg.write_enable()
+
+ ################################################################################
+ ##
+ ## Calculate the reference values
+ ##
+ ################################################################################
+ statisticsAccumulatedNode = []
+ for k in xrange(tc.nofFnNodes):
+ statisticsAccumulated = []
+ for i in range(c_nof_bf_units):
+ statisticsAccumulated.append(bf[k*c_nof_bf_units+i].calculate_beamlets(inputData, select_buf, weightsNodes[k][i], c_in_weight_w, c_blocks_per_sync))
+ statisticsAccumulatedNode.append(statisticsAccumulated)
+
+ ################################################################################
+ ##
+ ## Read out the beamlet statistics
+ ##
+ ################################################################################
+ # Wait a while before reading out the statistics
+ if tc.sim == True:
+ current_time = io.simIO.getSimTime()
+ wait_time = current_time[0] + 2*c_blocks_per_sync * c_nof_weights * c_clk_period
+ do_until_gt(io.simIO.getSimTime, wait_time, s_timeout=3600)
+ else:
+ tc.sleep(1)
+
+ tc.append_log(3, '>>>')
+ tc.append_log(2, '>>> Rep = %d, n = %d: Read the Beamlet Statistics of all bf_units' % (rep, n))
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '')
+
+ for k in xrange(tc.nofFnNodes):
+ beamlet_stats = []
+ for i in range(c_nof_bf_units):
+ beamlet_stats_bf_unit = bf[k*c_nof_bf_units+i].st.read_and_verify_stats(statisticsAccumulatedNode[k][i])
+ beamlet_stats.append(beamlet_stats_bf_unit)
+
+ # - Disable the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Disable the block generator')
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '')
+ bg.write_disable()
+
+ n+=1
+
+
+ ###############################################################################
+ # End
+ tc.set_section_id('')
+ tc.append_log(3, '')
+ tc.append_log(3, '>>>')
+ tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+ tc.append_log(3, '>>>')
+
+ sys.exit(tc.get_result())
\ No newline at end of file
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9a17b5469a9d708d073c235fda8650148a11db9e
--- /dev/null
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for fn_bf
+-- The DUT can be targeted at unb 0, fn 3 with the same Python scripts
+-- that are used on hardware.
+
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, bf_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE bf_lib.bf_pkg.ALL;
+
+ENTITY tb_unb1_fn_bf IS
+GENERIC(
+ -- TYPE t_c_bf IS RECORD
+ -- nof_signal_paths : POSITIVE; -- = 64
+ -- nof_input_streams : POSITIVE; -- = 16
+ -- nof_subbands : POSITIVE; -- = 24
+ -- nof_weights : POSITIVE; -- = 256
+ -- nof_bf_units : POSITIVE; -- = 4
+ -- in_dat_w : POSITIVE; -- = 16
+ -- in_weight_w : POSITIVE; -- = 16
+ -- bst_gain_w : INTEGER; -- = 1
+ -- bst_dat_w : POSITIVE; -- = 16
+ -- out_gain_w : INTEGER; -- = -5
+ -- out_dat_w : POSITIVE; -- = 8
+ -- stat_data_w : POSITIVE; -- = 56
+ -- stat_data_sz : POSITIVE; -- = 2
+ -- END RECORD;
+ g_bf : t_c_bf := (64, 16, 24, 256, 4, 16, 16, 1, 16, -5, 8, 56, 2)
+);
+END tb_unb1_fn_bf;
+
+ARCHITECTURE tb OF tb_unb1_fn_bf IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 3; -- Front node 3
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
+
+ CONSTANT c_cable_delay : TIME := 12 ns;
+ CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
+ CONSTANT c_clk_period : TIME := 1 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ -- DUT
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+
+ -- Model I2C sensor slaves as on the UniBoard
+ CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
+ CONSTANT c_fpga_temp : INTEGER := 60;
+ CONSTANT c_eth_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001"; -- MAX1618 address MID LOW
+ CONSTANT c_eth_temp : INTEGER := 40;
+ CONSTANT c_hot_swap_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100"; -- LTC4260 address L L L
+ CONSTANT c_hot_swap_R_sense : REAL := 0.01; -- = 10 mOhm on UniBoard
+
+ CONSTANT c_uniboard_current : REAL := 5.0; -- = assume 5.0 A on UniBoard
+ CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard
+ CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+
+ ------------------------------------------------------------------------------
+ -- 1GbE Loopback model
+ ------------------------------------------------------------------------------
+ eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_dut : ENTITY work.unb1_fn_bf
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_bf => g_bf
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp
+ );
+
+END tb;