starting with tb

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd

@@ -29,14 +29,15 @@
 --  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
 --  The output vector must be larger than the input vector.
 
-LIBRARY IEEE, dp_lib;
+LIBRARY IEEE, dp_lib, tech_ddr_lib;
 USE IEEE.std_logic_1164.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
 
 ENTITY ddrctrl_repack IS
   GENERIC (
-    g_in_data_w	  : NATURAL := 168;
-    g_out_data_w  : NATURAL := 576
+    g_tech_ddr    : t_c_tech_ddr;
+    g_in_data_w	  : NATURAL := 168
   );
   PORT (
     clk	     	    : IN  STD_LOGIC;
@@ -49,7 +50,8 @@ END ddrctrl_repack;
 
 ARCHITECTURE rtl OF ddrctrl_repack IS
 
-  CONSTANT k_c_v_w			    : NATURAL                               := g_out_data_w*2;
+  CONSTANT c_out_data_w     : NATURAL                               := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
+  CONSTANT k_c_v_w			    : NATURAL                               := c_out_data_w*2;
 
   SIGNAL  c_v_count			    : NATURAL                               := 0;
   SIGNAL  out_data_count		: NATURAL                               := 0;
@@ -65,24 +67,22 @@ BEGIN
 
     IF rising_edge(clk) THEN
 
-      IF ((g_in_data_w*(c_v_count+1))+a_of >= g_out_data_w*(out_data_count+1)) THEN								                                      -- if the input data exceeds the output data vector width
+      IF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) THEN								                                      -- if the input data exceeds the output data vector width
 
 	      IF (out_data_count = 1) THEN													                                                                         	-- if the input data exceeds c_v widt
-          ASSERT FALSE REPORT "1" SEVERITY NOTE;
-          a_of := a_of + (g_in_data_w*(c_v_count+1)) - (g_out_data_w*(out_data_count+1));							                                  -- check how much overflow there is and safe it in a_of
+          a_of := a_of + (g_in_data_w*(c_v_count+1)) - (c_out_data_w*(out_data_count+1));							                                  -- check how much overflow there is and safe it in a_of
         	out_of <= a_of;													                                                                                 		  -- set the output overflow to the overflow that maches the out_sosi.data vector
 	        c_v(k_c_v_w - 1 DOWNTO k_c_v_w-(g_in_data_w - a_of)) := in_data(g_in_data_w - a_of - 1 DOWNTO 0);			                        -- fill the rest of c_v untill the end
 	        c_v(a_of - 1 DOWNTO 0) := in_data(g_in_data_w - 1 DOWNTO g_in_data_w - a_of);							                                    -- fill the start of c_v untill the a_of
-	        out_sosi.data(g_out_data_w - 1 DOWNTO 0) <= c_v(k_c_v_w - 1 DOWNTO g_out_data_w);							                                -- fill out_sosi.data with 2nd part of c_v
+	        out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(k_c_v_w - 1 DOWNTO c_out_data_w);							                                -- fill out_sosi.data with 2nd part of c_v
 	        out_sosi.valid <= '1';													                                                          	                  -- out_sosi.valid 1
 	        c_v_count	<= 0; 													                                                                                   	-- reset counter
           out_data_count <= 0;													                                                                               	-- reset counter
 
 	      Else															                                                                                            	-- if the input data exceeds output data vector width but not the c_v vector widt
-          ASSERT FALSE REPORT "2" SEVERITY NOTE;
 	        c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); 	  -- fill c_v
 	        c_v_count <= c_v_count + 1;													                                                                          -- increase the counter of c_v with 1
-	        out_sosi.data(g_out_data_w - 1 DOWNTO 0) <= c_v(g_out_data_w - 1 DOWNTO 0);						                                        -- fill out_sosi.data with 1st part of c_v
+	        out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(c_out_data_w - 1 DOWNTO 0);						                                        -- fill out_sosi.data with 1st part of c_v
 	        out_sosi.valid <= '1';													                                                                              -- out_sosi.valid 1
 	        out_data_count <= out_data_count + 1;													                                                                -- increase the counter of out_sosi.data with 1
 	      END IF;

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd

@@ -35,8 +35,8 @@ USE common_lib.common_pkg.ALL;
 ENTITY tb_ddrctrl_repack IS
   GENERIC (
 
-    g_in_data_w	  : NATURAL := 168;
-    g_out_data_w  : NATURAL := 576
+    g_tech_ddr                : t_c_tech_ddr                            := c_tech_ddr4_8g_1600m;
+    g_in_data_w	              : NATURAL                                 := 168
 
   );
 END tb_ddrctrl_repack;
@@ -45,6 +45,7 @@ ARCHITECTURE tb OF tb_ddrctrl_repack IS
 
   CONSTANT  c_clk_freq        : NATURAL                                 := 200;     -- MHz
   CONSTANT  c_clk_period      : TIME                                    := (10**6 / c_clk_freq) * 1 ps;
+  CONSTANT  c_out_data_w      : NATURAL                                 := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
 
 
   SIGNAL    tb_end            : STD_LOGIC                               := '0';
@@ -83,18 +84,16 @@ BEGIN
 
   p_verify : PROCESS
   BEGIN
-    WAIT UNTIL rising_edge(clk);
-    IF rising_edge(clk) THEN
-      --check_data : FOR I IN 0 TO g_nof_streams - 1 LOOP
-        --ASSERT out_data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) = in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) REPORT "Data does not match, I = " & NATURAL'image(I) SEVERITY ERROR;
-      --END LOOP;
+    WAIT UNTIL rising_edge(out_sosi.valid);
+    IF rising_edge(out_sosi.valid) THEN
+        ASSERT out_sosi.data(c_out_data_w -1 DOWNTO 0) = iets REPORT "Data does not match, I = " SEVERITY NOTE;
     END IF;
   END PROCESS;
 
   u_ddrctrl_repack : ENTITY work.ddrctrl_repack
   GENERIC MAP (
-    g_in_data_w       => g_in_data_w,
-    g_out_data_w      => g_out_data_w
+    g_tech_ddr        => g_tech_ddr,
+    g_in_data_w       => g_in_data_w
   )
   PORT MAP (
     clk               => clk,