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Commit 738ca98e authored by Eric Kooistra's avatar Eric Kooistra
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Removed key modelsim_search_libraries, because it is now defined in hdltool_<toolset>.cfg

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applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg
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− 4
View file @ 738ca98e
...@@ -24,10 +24,6 @@ test_bench_files = ...@@ -24,10 +24,6 @@ test_bench_files =
[modelsim_project_file] [modelsim_project_file]
modelsim_copy_files = ../../src/hex hex modelsim_copy_files = ../../src/hex hex
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
[quartus_project_file] [quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
......
applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_bf_tp/hdllib.cfg
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− 4
View file @ 738ca98e
...@@ -26,10 +26,6 @@ modelsim_copy_files = ../../src/hex hex ...@@ -26,10 +26,6 @@ modelsim_copy_files = ../../src/hex hex
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
[quartus_project_file] [quartus_project_file]
synth_top_level_entity = apertif_unb1_fn_beamformer_bg_bf_tp synth_top_level_entity = apertif_unb1_fn_beamformer_bg_bf_tp
......
applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_tp/hdllib.cfg
+ 0
− 4
View file @ 738ca98e
...@@ -26,10 +26,6 @@ modelsim_copy_files = ../../src/hex hex ...@@ -26,10 +26,6 @@ modelsim_copy_files = ../../src/hex hex
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
[quartus_project_file] [quartus_project_file]
synth_top_level_entity = apertif_unb1_fn_beamformer_bg_tp synth_top_level_entity = apertif_unb1_fn_beamformer_bg_tp
......
applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
+ 0
− 4
View file @ 738ca98e
...@@ -27,10 +27,6 @@ modelsim_copy_files = ../../src/hex hex ...@@ -27,10 +27,6 @@ modelsim_copy_files = ../../src/hex hex
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
[quartus_project_file] [quartus_project_file]
synth_top_level_entity = apertif_unb1_fn_beamformer_transpose synth_top_level_entity = apertif_unb1_fn_beamformer_transpose
......
applications/apertif/designs/apertif_unb1_fn_bf_emu/hdllib.cfg
+ 0
− 4
View file @ 738ca98e
...@@ -16,10 +16,6 @@ test_bench_files = ...@@ -16,10 +16,6 @@ test_bench_files =
[modelsim_project_file] [modelsim_project_file]
modelsim_copy_files = src/hex hex modelsim_copy_files = src/hex hex
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
[quartus_project_file] [quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
......
libraries/base/reorder/hdllib.cfg
+ 0
− 4
View file @ 738ca98e
...@@ -37,10 +37,6 @@ test_bench_files = ...@@ -37,10 +37,6 @@ test_bench_files =
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
[quartus_project_file] [quartus_project_file]
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