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Commit 70caace2 authored by Eric Kooistra's avatar Eric Kooistra
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Added synthesis project for dp_bsn_align_v2.vhd to investigate M20K BRAM usage.

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1 merge request!254Corrected c_block_size_w, by using +1 to ensure that g_block_size that is...
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libraries/base/dp/hdllib.cfg
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......@@ -424,3 +424,5 @@ regression_test_vhdl =
[quartus_project_file]
quartus_copy_files =
$RADIOHDL_WORK/libraries/base/dp/quartus_unb2c quartus_unb2c
libraries/base/dp/quartus_unb2c/dp_bsn_align_v2.qpf 0 → 100644
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 19.4.0 Build 64 12/04/2019 SC Pro Edition
# Date created = 13:49:06 May 11, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "19.4"
DATE = "13:49:06 May 11, 2022"
# Revisions
PROJECT_REVISION = "dp_bsn_align_v2"
libraries/base/dp/quartus_unb2c/dp_bsn_align_v2.qsf 0 → 100644
+ 125
− 0
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###############################################################################
# Copyright 2022
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
###############################################################################
#
# Author: E. Kooistra, 11 May 2022
# Purpose: Synthesis of dp_bsn_align_v2 to investigate M20K BRAM usage
#
# Description:
# . Created dp_bsn_align_v2.qpf and qsf with GUI using run_quartus unb2c &
# . Use virtual pins so that it fits the FPGA, as explained in [1].
#
# References:
# [1] "Virtual Pin Assignments in a Partial Design", Apr 17, 2021,
# https://www.youtube.com/watch?v=QET0lC-jdAQ
set_global_assignment -name TOP_LEVEL_ENTITY dp_bsn_align_v2
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:49:06 MAY 11, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "19.4.0 Pro Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE 10AX115N2F45E2SG
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Used GUI to add the qip files that dp_bsn_align_v2 depends on:
set_global_assignment -name QIP_FILE ../../ip_arria10_e2sg_ram/ip_arria10_e2sg_ram_lib.qip
set_global_assignment -name QIP_FILE ../../tech_mult/tech_mult_lib.qip
set_global_assignment -name QIP_FILE ../../common_mult/common_mult_lib.qip
set_global_assignment -name QIP_FILE ../../tech_iobuf/tech_iobuf_lib.qip
set_global_assignment -name QIP_FILE ../../mm/mm_lib.qip
set_global_assignment -name QIP_FILE ../../tech_fifo/tech_fifo_lib.qip
set_global_assignment -name QIP_FILE ../../easics/easics_lib.qip
set_global_assignment -name QIP_FILE ../../technology/technology_lib.qip
set_global_assignment -name QIP_FILE ../../tech_memory/tech_memory_lib.qip
set_global_assignment -name QIP_FILE ../../common/common_lib.qip
set_global_assignment -name QIP_FILE ../dp_lib.qip
# Used GUI to add the ports of dp_bsn_align_v2 as virtual pins so that it fits the FPGA [1].
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].eop
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].sop
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].sync
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].valid
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].eop
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].sop
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].sync
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].valid
set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[0].rdval
set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[0].waitrequest
set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[1].rdval
set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[1].waitrequest
set_instance_assignment -name VIRTUAL_PIN ON -to mm_copi.rd
set_instance_assignment -name VIRTUAL_PIN ON -to mm_copi.wr
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.eop
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.sop
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.sync
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.valid
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].eop
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].sop
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].sync
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].valid
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].eop
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].sop
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].sync
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].valid
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].bsn
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].channel
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].data
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].empty
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].err
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].im
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].re
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].bsn
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].channel
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].data
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].empty
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].err
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].im
set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].re
set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[0].rddata
set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[1].rddata
set_instance_assignment -name VIRTUAL_PIN ON -to mm_copi.address
set_instance_assignment -name VIRTUAL_PIN ON -to mm_copi.wrdata
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.bsn
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.channel
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.data
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.empty
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.err
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.im
set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.re
set_instance_assignment -name VIRTUAL_PIN ON -to node_index
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].bsn
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].channel
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].data
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].empty
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].err
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].im
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].re
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].bsn
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].channel
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].data
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].empty
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].err
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].im
set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].re
set_instance_assignment -name VIRTUAL_PIN ON -to stream_en_arr
set_instance_assignment -name VIRTUAL_PIN ON -to stream_replaced_cnt_arr
set_instance_assignment -name VIRTUAL_PIN ON -to dp_rst
libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
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− 5
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......@@ -57,12 +57,12 @@ USE work.dp_stream_pkg.ALL;
ENTITY dp_bsn_align_v2 IS
GENERIC (
g_nof_streams : NATURAL; -- >= 2, number of input and output streams
g_bsn_latency_max : NATURAL; -- maximum travel latency of a remote block in number of block periods T_blk
g_nof_aligners_max : POSITIVE := 1; -- 1 when only align at last node, > 1 when align at every intermediate node
g_block_size : NATURAL := 32; -- > 1, g_block_size=1 is not supported
g_nof_streams : NATURAL := 2; -- >= 2, number of input and output streams
g_bsn_latency_max : NATURAL := 2; -- maximum travel latency of a remote block in number of block periods T_blk
g_nof_aligners_max : POSITIVE := 16; -- 1 when only align at last node, > 1 when align at every intermediate node
g_block_size : NATURAL := 1024; -- > 1, g_block_size=1 is not supported
g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN
g_data_w : NATURAL; -- number of bits in sosi data
g_data_w : NATURAL := 36; -- number of bits in sosi data
g_data_replacement_value : INTEGER := 0; -- output sosi data value for missing input blocks
g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP
g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
......
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