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RTSD
HDL
Commits
70b94c09
Commit
70b94c09
authored
10 years ago
by
Eric Kooistra
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Must instantiate the IP as components instead of as entities.
parent
9e9a62c4
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libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
+7
-7
7 additions, 7 deletions
.../technology/transceiver/tech_transceiver_gx_stratixiv.vhd
with
7 additions
and
7 deletions
libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
+
7
−
7
View file @
70b94c09
...
...
@@ -135,7 +135,7 @@ BEGIN
gen_tr
:
IF
g_tx
=
TRUE
AND
g_rx
=
TRUE
GENERATE
--Generate duplex transceivers
gen_32b
:
IF
g_data_w
=
32
GENERATE
u_gx
:
ENTITY
ip_stratixiv_lib
.
ip_stratixiv_hssi_gx_32b_generic
u_gx
:
ip_stratixiv_hssi_gx_32b_generic
GENERIC
MAP
(
g_mbps
=>
g_mbps
,
starting_channel_number
=>
i
*
4
--Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
...
...
@@ -181,7 +181,7 @@ BEGIN
END
GENERATE
;
gen_16b
:
IF
g_data_w
=
16
GENERATE
u_gx
:
ENTITY
ip_stratixiv_lib
.
ip_stratixiv_hssi_gx_16b
u_gx
:
ip_stratixiv_hssi_gx_16b
GENERIC
MAP
(
starting_channel_number
=>
i
*
4
--Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
)
--Reconfig megawizard: regenerate with 'number of channels' = 4*nof_gx
...
...
@@ -225,7 +225,7 @@ BEGIN
gen_rx
:
IF
g_tx
=
FALSE
AND
g_rx
=
TRUE
GENERATE
--Generate receivers only
gen_32b
:
IF
g_data_w
=
32
GENERATE
u_rx
:
ENTITY
ip_stratixiv_lib
.
ip_stratixiv_hssi_rx_32b_generic
u_rx
:
ip_stratixiv_hssi_rx_32b_generic
GENERIC
MAP
(
g_mbps
=>
g_mbps
,
starting_channel_number
=>
i
*
4
--Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
...
...
@@ -251,7 +251,7 @@ BEGIN
END
GENERATE
;
gen_16b
:
IF
g_data_w
=
16
GENERATE
u_rx
:
ENTITY
ip_stratixiv_lib
.
ip_stratixiv_hssi_rx_16b
u_rx
:
ip_stratixiv_hssi_rx_16b
GENERIC
MAP
(
starting_channel_number
=>
i
*
4
--Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
)
--Reconfig megawizard: regenerate with 'number of channels' = 4*nof_gx
...
...
@@ -289,7 +289,7 @@ BEGIN
gen_tx
:
IF
g_tx
=
TRUE
AND
g_rx
=
FALSE
GENERATE
gen_32b
:
IF
g_data_w
=
32
GENERATE
u_tx
:
ENTITY
ip_stratixiv_lib
.
ip_stratixiv_hssi_tx_32b_generic
u_tx
:
ip_stratixiv_hssi_tx_32b_generic
GENERIC
MAP
(
g_mbps
=>
g_mbps
)
...
...
@@ -308,7 +308,7 @@ BEGIN
END
GENERATE
;
gen_16b
:
IF
g_data_w
=
16
GENERATE
u_tx
:
ENTITY
ip_stratixiv_lib
.
ip_stratixiv_hssi_tx_16b
u_tx
:
ip_stratixiv_hssi_tx_16b
PORT
MAP
(
-- Clocks, in
pll_inclk
=>
tr_clk
,
...
...
@@ -486,7 +486,7 @@ BEGIN
-- ALTGX_RECONFIG Megafunction
------------------------------------------------------------------------------
u_gxb_reconfig
:
ENTITY
ip_stratixiv_lib
.
ip_stratixiv_gxb_reconfig
-- Create one gxb_reconfig module for all ALTGX instances
u_gxb_reconfig
:
ip_stratixiv_gxb_reconfig
-- Create one gxb_reconfig module for all ALTGX instances
GENERIC
MAP
(
g_nof_gx
=>
g_nof_gx
,
g_fromgxb_bus_w
=>
c_reconf_fromgxb_bus_w
,
-- = 17
...
...
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