add ip files and changed code to get minimal wroking design

...n_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd

...s_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.bsf

...s_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.cmp

..._arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.html

...s_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.qgsynthc

...s_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.qip

...s_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.sopcinfo

...s_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.xml

..._arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_bb.v

...b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_generation.rpt

...rts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_inst.v

...s_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_inst.vhd

...s_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.vhd

.../qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip

...c3_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd

...b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.bsf

...b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.cmp

..._sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.html

..._reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.qgsynthc

...b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.qip