add ip files and changed code to get minimal wroking design

...pga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_bb.v

...ens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_generation.rpt

...a_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_inst.v

...temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_inst.vhd

...emp_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.vhd

...ts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip

...pga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd

...oltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.bsf

...oltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.cmp

...ltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.html

...e_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.qgsynthc

...oltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.qip

...e_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.sopcinfo

...oltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.xml

...ltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_bb.v

.../qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_generation.rpt

...age_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_inst.v

...e_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_inst.vhd

..._sens/synth/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.vhd

...ys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip