add ip files and changed code to get minimal wroking design

...0g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.cmp

...g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.html

...fp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.qgsynthc

...0g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.qip

...fp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.sopcinfo

...0g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.xml

...g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_bb.v

...g/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_generation.rpt

...qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_inst.v

...fp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_inst.vhd

...p_ring/synth/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.vhd

..._arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip

...g_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd

...fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.bsf

...fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.cmp

...pga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.html

...temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.qgsynthc

...fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.qip

...temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.sopcinfo

...fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.xml