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Commit 7053afa9 authored by Eric Kooistra's avatar Eric Kooistra
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Moved build_dir_sim and build_dir_synth keys from local hdllib.cfg to central hdltool.cfg

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libraries/technology/10gbase_r/hdllib.cfg
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View file @ 7053afa9
...@@ -13,9 +13,6 @@ hdl_lib_uses_sim = ...@@ -13,9 +13,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files = synth_files =
sim_10gbase_r.vhd sim_10gbase_r.vhd
tech_10gbase_r_component_pkg.vhd tech_10gbase_r_component_pkg.vhd
......
libraries/technology/ddr/hdllib.cfg
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...@@ -11,9 +11,6 @@ hdl_lib_uses_sim = ...@@ -11,9 +11,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files = synth_files =
tech_ddr_pkg.vhd tech_ddr_pkg.vhd
tech_ddr_component_pkg.vhd tech_ddr_component_pkg.vhd
......
libraries/technology/eth_10g/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files = synth_files =
tech_eth_10g_stratixiv.vhd tech_eth_10g_stratixiv.vhd
tech_eth_10g_arria10.vhd tech_eth_10g_arria10.vhd
......
libraries/technology/fifo/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files = synth_files =
tech_fifo_component_pkg.vhd tech_fifo_component_pkg.vhd
tech_fifo_sc.vhd tech_fifo_sc.vhd
......
libraries/technology/flash/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -8,9 +8,6 @@ hdl_lib_uses_sim = ...@@ -8,9 +8,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files = synth_files =
tech_flash_component_pkg.vhd tech_flash_component_pkg.vhd
tech_flash_asmi_parallel.vhd tech_flash_asmi_parallel.vhd
......
libraries/technology/iobuf/hdllib.cfg
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View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files = synth_files =
tech_iobuf_component_pkg.vhd tech_iobuf_component_pkg.vhd
tech_iobuf_ddio_in.vhd tech_iobuf_ddio_in.vhd
......
libraries/technology/ip_arria10/ddio/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/ddio/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/ddio/compile_ip.tcl
......
libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
......
libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
......
libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
......
libraries/technology/ip_arria10/fifo/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files = synth_files =
ip_arria10_fifo_sc.vhd ip_arria10_fifo_sc.vhd
ip_arria10_fifo_dc.vhd ip_arria10_fifo_dc.vhd
......
libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
......
libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
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View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
......
libraries/technology/ip_arria10/mac_10g/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
......
libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
......
libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
......
libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
......
libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
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View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
......
libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
......
libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
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− 3
View file @ 7053afa9
...@@ -5,9 +5,6 @@ hdl_lib_uses_sim = ...@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
......
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