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Commit 7053afa9 authored by Eric Kooistra's avatar Eric Kooistra
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Moved build_dir_sim and build_dir_synth keys from local hdllib.cfg to central hdltool.cfg

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libraries/technology/ip_arria10/ram/hdllib.cfg
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View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_arria10_true_dual_port_ram_dual_clock.vhd
ip_arria10_simple_dual_port_ram_dual_clock.vhd
......
libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
......
libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
......
libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
......
libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
......
libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
......
libraries/technology/ip_stratixiv/ddio/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_stratixiv_ddio_in.vhd
ip_stratixiv_ddio_out.vhd
......
libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
+ 0
− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
......
libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
......
libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
......
libraries/technology/ip_stratixiv/fifo/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_stratixiv_fifo_dc_mixed_widths.vhd
ip_stratixiv_fifo_dc.vhd
......
libraries/technology/ip_stratixiv/flash/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_stratixiv_asmi_parallel.vhd
ip_stratixiv_remote_update.vhd
......
libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
......
libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+ 0
− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
$RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
......
libraries/technology/ip_stratixiv/pll/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_stratixiv_pll_clk200.vhd
ip_stratixiv_pll_clk200_p6.vhd
......
libraries/technology/ip_stratixiv/pll_clk25/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_stratixiv_pll_clk25.vhd
......
libraries/technology/ip_stratixiv/ram/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_stratixiv_ram_crwk_crw.vhd
ip_stratixiv_ram_crw_crw.vhd
......
libraries/technology/ip_stratixiv/transceiver/hdllib.cfg
+ 0
− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_stratixiv_gxb_reconfig_v91_2.vhd
ip_stratixiv_gxb_reconfig_v91_4.vhd
......
libraries/technology/ip_stratixiv/tse_sgmii_gx/hdllib.cfg
+ 0
− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
test_bench_files =
......
libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
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− 3
View file @ 7053afa9
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
test_bench_files =
......
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