-Cleaned code.

libraries/dsp/st/src/vhdl/st_histogram.vhd

@@ -156,9 +156,6 @@ ARCHITECTURE rtl OF st_histogram IS
   SIGNAL bin_arbiter_rd_ram_pointer     : STD_LOGIC;
   SIGNAL prv_bin_arbiter_rd_ram_pointer : STD_LOGIC;
 
-  SIGNAL read_allowed                   : BOOLEAN;
-  SIGNAL prv_read_allowed               : BOOLEAN;
-
   SIGNAL nxt_bin_arbiter_wr_mosi        : t_mem_mosi;
   SIGNAL bin_arbiter_wr_mosi            : t_mem_mosi;
   SIGNAL bin_arbiter_rd_mosi            : t_mem_mosi;
@@ -389,22 +386,11 @@ BEGIN
   --           bin_arbiter_rd_mosi (rd requests to RAM)
   --           bin_reader_miso (carries the bins requested by bin_reader)
   -------------------------------------------------------------------------------
-  -- Really simple arbitration: always allow writes, only allow reads when possible (rd_addr != wr_addr).
-  read_allowed <= FALSE WHEN bin_writer_mosi.wr='1' AND bin_reader_mosi.rd='1' AND bin_writer_mosi.address=bin_reader_mosi.address ELSE TRUE;
-  -- save previous read_allowed
-  p_prv_read_allowed: PROCESS(dp_rst, dp_clk) IS
-  BEGIN
-    IF dp_rst='1' THEN
-      prv_read_allowed <= FALSE;
-    ELSIF RISING_EDGE(dp_clk) THEN
-      prv_read_allowed <= read_allowed;
-    END IF;
-  END PROCESS;
 
   -- Forward MOSI buses
   -- . RD MOSI
   bin_arbiter_rd_mosi.wr      <= '0';
-  bin_arbiter_rd_mosi.rd      <= bin_reader_mosi.rd WHEN read_allowed ELSE '0';
+  bin_arbiter_rd_mosi.rd      <= bin_reader_mosi.rd;
   bin_arbiter_rd_mosi.address <= bin_reader_mosi.address;
   -- . WR MOSI
   bin_arbiter_wr_mosi.rd      <= '0';