-Cleaned code.

libraries/dsp/st/src/vhdl/st_histogram.vhd

@@ -200,13 +200,6 @@ ARCHITECTURE rtl OF st_histogram IS
   SIGNAL nxt_ram_clearing      : STD_LOGIC;
 
 
-
-
-SIGNAL debug1 : STD_LOGIC;
-SIGNAL debug2 : STD_LOGIC;
-
-
-
 BEGIN 
 
   -------------------------------------------------------------------------------
@@ -346,7 +339,6 @@ BEGIN
   bin_reader_mosi.wrdata  <= (OTHERS=>'0');
   bin_reader_mosi.wr      <= '0';
   bin_reader_mosi.rd      <= snk_in_reg.valid;
---  bin_reader_mosi.address <= RESIZE_UVEC(ram_pointer & snk_in_data, c_word_w); 
   bin_reader_mosi.address <= RESIZE_UVEC(ram_pointer & snk_in_reg.data(c_ram_adr_w-1 DOWNTO 0), c_word_w); 
 
   p_prv_bin_reader_mosi : PROCESS(dp_clk, dp_rst) IS
@@ -366,16 +358,12 @@ BEGIN
   bin_reader_to_writer_mosi.address <= prv_bin_reader_mosi.address;
   nxt_bin_reader_to_writer_count    <= TO_UINT(snk_in_reg.channel); -- Use register (_nxt) to align count with rdval instead of snk_in_reg.valid
 
+
   -------------------------------------------------------------------------------
   -- bin_writer : Increment the bin, forward write request to bin_arbiter
   -- . Input  : bin_reader_to_writer_mosi (from bin_reader = bin + bin count)
   -- . Output : bin_writer_mosi (to bin_arbiter = bin + incremented bin count)
   -------------------------------------------------------------------------------
---  bin_writer_mosi.rd      <= '0';
---  bin_writer_mosi.wr      <= bin_reader_to_writer_mosi.wr;
---  bin_writer_mosi.address <= bin_reader_to_writer_mosi.address;
---  bin_writer_mosi.wrdata  <= INCR_UVEC(bin_reader_to_writer_mosi.wrdata, 1) WHEN bin_reader_to_writer_mosi.wr='1' ELSE bin_reader_to_writer_mosi.wrdata; 
-
   nxt_bin_writer_mosi.rd      <= '0';
   nxt_bin_writer_mosi.wr      <= bin_reader_to_writer_mosi.wr;
   nxt_bin_writer_mosi.address <= bin_reader_to_writer_mosi.address;
@@ -424,30 +412,7 @@ BEGIN
   bin_arbiter_wr_mosi.wrdata  <= bin_writer_mosi.wrdata;
   bin_arbiter_wr_mosi.address <= bin_writer_mosi.address;
 
-  -- Loop back the WR data to the RD side when read was not allowed or on second read of same address
-  p_bin_reader_miso : PROCESS(prv_bin_reader_mosi, prv_read_allowed, bin_reader_mosi, bin_writer_mosi, read_allowed, bin_arbiter_rd_miso) IS
-  BEGIN
-    debug1 <= '0';
-    debug2 <= '0';
-    bin_reader_miso <= bin_arbiter_rd_miso;
---    IF prv_bin_reader_mosi.rd = '1' AND prv_read_allowed = FALSE THEN
---      -- Fake succesful readback when read was not allowed
---      bin_reader_miso.rdval  <= '1';
---      bin_reader_miso.rddata <= bin_writer_mosi.wrdata;
---      debug1 <= '1';
---    ELSIF read_allowed = TRUE THEN
---      bin_reader_miso <= bin_arbiter_rd_miso;
---    ELSIF (prv_bin_reader_mosi.rd = '1' AND bin_reader_mosi.rd='1') AND (prv_bin_reader_mosi.address=bin_reader_mosi.address) THEN
---      -- 2 reads on same address in row: 2nd read is outdated so return wrdata here
---      debug2 <= '1';
---      bin_reader_miso.rdval  <= '1';
---      bin_reader_miso.rddata <= bin_writer_mosi.wrdata;
---    END IF;
-  END PROCESS;
-
-  -- 1) Read bin from RAM (MOSI)
-  -- 2) Read bin value valid (MISO), increment bin value
-  -- 3) Write bin to RAM (MOSI)
+  bin_reader_miso <= bin_arbiter_rd_miso;
 
 
   -------------------------------------------------------------------------------
@@ -546,21 +511,8 @@ BEGIN
 
   -------------------------------------------------------------------------------
   -- Expose the MM buses to the user
-  -- . apply address correction if snk_in carries signed data
   -------------------------------------------------------------------------------
   ram_miso <= histogram_rd_miso;
-  
---  gen_unsiged: IF g_data_type="unsigned" GENERATE
-    histogram_rd_mosi <= ram_mosi;
---  END GENERATE;
-
---  gen_signed: IF g_data_type="signed" GENERATE
---    p_addr_swap: PROCESS(ram_mosi) IS
---    BEGIN
---      histogram_rd_mosi <= ram_mosi;
---      histogram_rd_mosi.address    <= ram_mosi.address;
---      histogram_rd_mosi.address(g_data_w-1) <= NOT ram_mosi.address(g_data_w-1); -- Invert MS address bit
---    END PROCESS;
---  END GENERATE;
+  histogram_rd_mosi <= ram_mosi;
 
 END rtl;