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Commit 6b871f36 authored by Eric Kooistra's avatar Eric Kooistra
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Added verification of RO block_size. Added verification of BSN high word monitoring.

parent c22f5837
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1 merge request!132Renamed proc_dp_verify_sync_v2() into overloaded proc_dp_verify_sync() and...
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libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+ 83
− 8
View file @ 6b871f36
......@@ -23,7 +23,7 @@
-- Usage:
-- > as 5
-- > run -all
-- . View *_64 BSN values as radix hex in Wave window to recognize BSN hi word.
LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
......@@ -46,7 +46,9 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_sync_scheduler IS
CONSTANT c_dp_clk_period : TIME := 10 ns;
CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
CONSTANT c_nof_input_sync : NATURAL := 5;
CONSTANT c_report_note : BOOLEAN := FALSE; -- Use TRUE for tb debugging, else FALSE to keep Transcript window more empty
CONSTANT c_nof_input_sync : NATURAL := 10;
CONSTANT c_nof_block_per_input_sync : NATURAL := 17;
CONSTANT c_nof_block_per_output_sync : NATURAL := 5;
CONSTANT c_block_size : NATURAL := 10;
......@@ -55,6 +57,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_sync_scheduler IS
-- DUT settings
CONSTANT c_bsn_w : NATURAL := 40;
CONSTANT c_bsn_hi_value : NATURAL := 23;
CONSTANT c_ctrl_interval_size : NATURAL := c_nof_block_per_output_sync * c_block_size;
CONSTANT c_ctrl_start_bsn_lo : NATURAL := 19;
CONSTANT c_ctrl_start_bsn_hi : NATURAL := 17;
......@@ -75,12 +78,16 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_sync_scheduler IS
SIGNAL mon_current_input_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_input_bsn_at_sync_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_output_sync_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_block_size : NATURAL;
SIGNAL stimuli_sosi : t_dp_sosi;
SIGNAL in_sosi : t_dp_sosi;
SIGNAL out_sosi : t_dp_sosi;
SIGNAL out_start : STD_LOGIC;
SIGNAL out_enable : STD_LOGIC;
SIGNAL verify_bsn_hi : STD_LOGIC := '0';
BEGIN
dp_clk <= (NOT dp_clk) OR tb_end AFTER c_dp_clk_period/2;
......@@ -102,6 +109,15 @@ BEGIN
---------------------------------------------------------------------------
-- Initial check
---------------------------------------------------------------------------
-- . Read mon_block_size
proc_mem_mm_bus_rd(11, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_block_size <= TO_UINT(reg_miso.rddata(c_word_w-1 DOWNTO 0));
-- . Verify mon_block_size
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_block_size = c_block_size REPORT "Wrong block_size." SEVERITY ERROR;
-- . Read mon_output_enable
proc_mem_mm_bus_rd(8, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
......@@ -217,7 +233,9 @@ BEGIN
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_current_input_bsn_64(2*c_word_w-1 DOWNTO c_word_w) <= reg_miso.rddata(c_word_w-1 DOWNTO 0);
proc_common_wait_some_cycles(mm_clk, 1);
IF c_report_note THEN
REPORT "mon_current_input_bsn : " & int_to_str(v_bsn) & ", " & int_to_str(TO_UINT(mon_current_input_bsn_64)) SEVERITY NOTE;
END IF;
ASSERT v_bsn < TO_UINT(mon_current_input_bsn_64) REPORT "DUT mon_current_input_bsn is not incrementing." SEVERITY ERROR;
-- . Check mon_input_bsn_at_sync_64
......@@ -229,7 +247,9 @@ BEGIN
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_input_bsn_at_sync_64(2*c_word_w-1 DOWNTO c_word_w) <= reg_miso.rddata(c_word_w-1 DOWNTO 0);
proc_common_wait_some_cycles(mm_clk, 1);
IF c_report_note THEN
REPORT "mon_input_bsn_at_sync : " & int_to_str(v_bsn) & ", " & int_to_str(TO_UINT(mon_input_bsn_at_sync_64)) SEVERITY NOTE;
END IF;
ASSERT v_bsn < TO_UINT(mon_input_bsn_at_sync_64) REPORT "DUT mon_input_bsn_at_sync is not incrementing." SEVERITY ERROR;
ASSERT (TO_UINT(mon_input_bsn_at_sync_64) - v_bsn) MOD c_nof_block_per_input_sync = 0 REPORT "TB input_sync interval is not correct." SEVERITY ERROR;
......@@ -242,10 +262,53 @@ BEGIN
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_output_sync_bsn_64(2*c_word_w-1 DOWNTO c_word_w) <= reg_miso.rddata(c_word_w-1 DOWNTO 0);
proc_common_wait_some_cycles(mm_clk, 1);
IF c_report_note THEN
REPORT "mon_output_sync_bsn : " & int_to_str(v_bsn) & ", " & int_to_str(TO_UINT(mon_output_sync_bsn_64)) SEVERITY NOTE;
END IF;
ASSERT v_bsn < TO_UINT(mon_output_sync_bsn_64) REPORT "DUT mon_output_sync_bsn is not incrementing." SEVERITY ERROR;
ASSERT (TO_UINT(mon_output_sync_bsn_64) - v_bsn) MOD c_nof_block_per_output_sync = 0 REPORT "DUT output_sync interval is not correct." SEVERITY ERROR;
---------------------------------------------------------------------------
-- Verify BSN hi word
---------------------------------------------------------------------------
-- . wait until input block boundary
proc_common_wait_until_high(dp_clk, stimuli_sosi.sop);
verify_bsn_hi <= '1';
proc_common_wait_some_cycles(dp_clk, c_block_size*c_nof_block_per_input_sync * 2);
-- . Read mon_current_input_bsn_64
proc_mem_mm_bus_rd(4, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_current_input_bsn_64(c_word_w-1 DOWNTO 0) <= reg_miso.rddata(c_word_w-1 DOWNTO 0);
proc_mem_mm_bus_rd(5, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_current_input_bsn_64(2*c_word_w-1 DOWNTO c_word_w) <= reg_miso.rddata(c_word_w-1 DOWNTO 0);
-- . Read mon_input_bsn_at_sync_64
proc_mem_mm_bus_rd(6, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_input_bsn_at_sync_64(c_word_w-1 DOWNTO 0) <= reg_miso.rddata(c_word_w-1 DOWNTO 0);
proc_mem_mm_bus_rd(7, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_input_bsn_at_sync_64(2*c_word_w-1 DOWNTO c_word_w) <= reg_miso.rddata(c_word_w-1 DOWNTO 0);
-- . Read mon_output_sync_bsn_64
proc_mem_mm_bus_rd(9, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_output_sync_bsn_64(c_word_w-1 DOWNTO 0) <= reg_miso.rddata(c_word_w-1 DOWNTO 0);
proc_mem_mm_bus_rd(10, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_output_sync_bsn_64(2*c_word_w-1 DOWNTO c_word_w) <= reg_miso.rddata(c_word_w-1 DOWNTO 0);
proc_common_wait_some_cycles(mm_clk, 1);
-- The out_sosi.bsn will not reach the c_bsn_hi_value, because the
-- dp_bsn_sync_scheduler will be busy trying to catch up, see
-- nxt_r.update_bsn = '1' in dp_bsn_sync_scheduler.vhd. Therefore
-- expected mon_output_sync_bsn_64 hi value is still 0.
ASSERT c_bsn_hi_value = TO_UINT(mon_current_input_bsn_64(2*c_word_w-1 DOWNTO c_word_w)) REPORT "Wrong mon_current_input_bsn high word." SEVERITY ERROR;
ASSERT c_bsn_hi_value = TO_UINT(mon_input_bsn_at_sync_64(2*c_word_w-1 DOWNTO c_word_w)) REPORT "Wrong mon_input_bsn_at_sync high word." SEVERITY ERROR;
ASSERT 0 = TO_UINT(mon_output_sync_bsn_64( 2*c_word_w-1 DOWNTO c_word_w)) REPORT "Wrong mon_output_sync_bsn high word." SEVERITY ERROR;
---------------------------------------------------------------------------
-- Disable and verify DUT output
---------------------------------------------------------------------------
......@@ -267,16 +330,28 @@ BEGIN
ASSERT mon_output_enable = '0' REPORT "DUT mon_output_enable is not diabled." SEVERITY ERROR;
ASSERT out_enable = '0' REPORT "DUT output_enable is not enabled." SEVERITY ERROR;
---------------------------------------------------------------------------
-- End of test
---------------------------------------------------------------------------
proc_common_wait_until_high(dp_clk, stimuli_end);
tb_end <= '1';
WAIT;
END PROCESS;
------------------------------------------------------------------------------
-- Streaming stimuli
------------------------------------------------------------------------------
p_in_sosi : PROCESS(stimuli_sosi, verify_bsn_hi)
BEGIN
in_sosi <= stimuli_sosi;
IF verify_bsn_hi = '1' THEN
-- Set hi word of input BSN
in_sosi.bsn(2*c_word_w-1 DOWNTO c_word_w) <= TO_UVEC(c_bsn_hi_value, c_word_w);
END IF;
END PROCESS;
-- Generate data blocks with input sync
u_stimuli : ENTITY work.dp_stream_stimuli
GENERIC MAP (
......@@ -321,7 +396,7 @@ BEGIN
reg_miso => reg_miso,
-- Streaming
in_sosi => stimuli_sosi,
in_sosi => in_sosi,
out_sosi => out_sosi,
out_start => out_start,
out_enable => out_enable
......
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