Added monitor RO field for g_block_size.

libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd

@@ -32,6 +32,7 @@
 --   8     [0]      RO  boolean   mon_output_enable, '1' is on, '0' is FALSE is off
 --   9  [31:0]      RO   uint64   mon_output_sync_bsn[31:0]
 --  10  [31:0]      RO            mon_output_sync_bsn[63:32]
+--  11  [31:0]      RO   uint32   block_size[31:0]
 --
 -- * Do not use reg_wr_arr[0] in dp_clk domain to detect ctrl_enable_evt,
 --   because reg_wr_arr pulses occur before the reg_wr data arrives in the
@@ -91,7 +92,7 @@ ARCHITECTURE str OF mmp_dp_bsn_sync_scheduler IS
   --   dat_w     : NATURAL;
   --   nof_dat   : NATURAL;    -- optional, nof dat words <= 2**adr_w
   --   init_sl   : STD_LOGIC;  -- optional, init all dat words to std_logic '0', '1' or 'X'
-  CONSTANT c_mm_reg         : t_c_mem := (1, 4, c_word_w, 11, '0');
+  CONSTANT c_mm_reg         : t_c_mem := (1, 4, c_word_w, 12, '0');
 
   SIGNAL reg_wr_arr         : STD_LOGIC_VECTOR(c_mm_reg.nof_dat               -1 DOWNTO 0);
   SIGNAL reg_wr             : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
@@ -158,6 +159,7 @@ BEGIN
   reg_rd(                      8*c_word_w) <= mon_output_enable;
   reg_rd(10*c_word_w-1 DOWNTO  9*c_word_w) <= rd_output_sync_bsn_64(    c_word_w-1 DOWNTO        0);  -- low word
   reg_rd(11*c_word_w-1 DOWNTO 10*c_word_w) <= rd_output_sync_bsn_64(  2*c_word_w-1 DOWNTO c_word_w);  -- high word
+  reg_rd(12*c_word_w-1 DOWNTO 11*c_word_w) <= TO_UVEC(g_block_size, c_word_w);
 
   u_common_reg_r_w_dc : ENTITY common_lib.common_reg_r_w_dc
   GENERIC MAP (