Define separate io_ddr_core and io_ddr_driver peripherals.

libraries/io/ddr/ddr.peripheral.yaml

@@ -6,14 +6,14 @@ hdl_library_name: ddr
 hdl_library_description: "Double data rate memory"
 
 peripherals:
-  - peripheral_name: io_ddr    # pi_io_ddr.py
-    peripheral_description: "DDR controller"
+  - peripheral_name: io_ddr_core
+    peripheral_description: "DDR controller core"
     mm_ports:
-      # MM port for io_ddr.vhd + io_ddr_reg.vhd
-      - mm_port_name: REG_IO_DDR
+      # MM port for io_ddr.vhd core
+      - mm_port_name: REG_IO_DDR_CORE
         mm_port_type: REG
-        mm_port_span: 8 * MM_BUS_SIZE
-        mm_port_description: "DDR controller registers."
+        mm_port_span: 8 * MM_BUS_SIZE  # span 4 is enough, but allocate same span as for REG_IO_DDR_DRIVER
+        mm_port_description: "DDR controller core registers."
         number_of_mm_ports: 1
         fields:
           # Register part of io_ddr.vhd for status of DDR4 interface
@@ -38,7 +38,80 @@ peripherals:
               field_description: "Read FIFO full bit & Write FIFO full bit, read both bits together because they get cleared upon read"
               address_offset: 3 * MM_BUS_SIZE
               access_mode: RO
-          # Register part of io_ddr_reg.vhd used in mms_io_ddr.vhd for write and read access to DDR memory via MM
+
+  - peripheral_name: io_ddr_driver
+    peripheral_description: "DDR controller driver"
+    mm_ports:
+      # MM port for io_ddr_reg.vhd driver
+      - mm_port_name: REG_IO_DDR_DRIVER
+        mm_port_type: REG
+        mm_port_span: 8 * MM_BUS_SIZE
+        mm_port_description: "DDR controller driver registers."
+        number_of_mm_ports: 1
+        fields:
+          # Register part of io_ddr_reg.vhd driver used in mms_io_ddr.vhd for write and read access to DDR memory via MM
+          - - field_name: reg_burstbegin
+              field_description: "Start write or read access to DDR when reg_burstbegin = 1."
+              address_offset: 0 * MM_BUS_SIZE
+              access_mode: WO
+          - - field_name: reg_wr_not_rd
+              field_description: "Set read / write mode. reg_wr_not_rd = 1 = write mode, reg_wr_not_rd = 0 = read mode."
+              address_offset: 1 * MM_BUS_SIZE
+              access_mode: WO
+          - - field_name: reg_done
+              field_description: "reg_done = 1 when memory access is finished."
+              address_offset: 2 * MM_BUS_SIZE
+              access_mode: RO
+          - - field_name: reg_address
+              field_description: "Start address for memory access."
+              address_offset: 5 * MM_BUS_SIZE
+              access_mode: WO
+          - - field_name: reg_burstsize
+              field_description: "Access size for memory access"
+              address_offset: 6 * MM_BUS_SIZE
+              access_mode: WO
+          - - field_name: reg_flush
+              field_description: |
+                "Flush the write FIFO
+                 The user input to the write FIFO should be off. Internally the method waits sufficient us to
+                 ensure that the write FIFO is read empty."
+              address_offset: 7 * MM_BUS_SIZE
+
+  - peripheral_name: io_ddr    # pi_io_ddr.py
+    peripheral_description: "DDR controller core + driver"
+    mm_ports:
+      # MM port for io_ddr.vhd (= core) + io_ddr_reg.vhd (= driver)
+      - mm_port_name: REG_IO_DDR  # = REG_IO_DDR_CORE & REG_IO_DDR_DRIVER
+        mm_port_type: REG
+        mm_port_span: 16 * MM_BUS_SIZE
+        mm_port_description: "DDR controller core + driver registers."
+        number_of_mm_ports: 1
+        fields:
+          # Same as REG_IO_DDR_CORE:
+          # Register part of io_ddr.vhd core for status of DDR4 interface
+          - - field_name: reg_io_ddr
+              field_description: |
+                "IO DDR status bits concatenated:
+                 ddr_gigabytes[7:0] &
+                 ctlr_nof_bytes_per_word[7:0] &
+                 ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail      & ctlr_tech_miso.cal_ok &
+                 ctlr_rst_out_i    & ctlr_wr_flush_en     & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done"
+              address_offset: 0 * MM_BUS_SIZE
+              access_mode: RO
+          - - field_name: reg_rd_fifo_used
+              field_description: "Read FIFO fill level."
+              address_offset: 1 * MM_BUS_SIZE
+              access_mode: RO
+          - - field_name: reg_wr_fifo_used
+              field_description: "Write FIFO fill level."
+              address_offset: 2 * MM_BUS_SIZE
+              access_mode: RO
+          - - field_name: reg_fifo_full
+              field_description: "Read FIFO full bit & Write FIFO full bit, read both bits together because they get cleared upon read"
+              address_offset: 3 * MM_BUS_SIZE
+              access_mode: RO
+          # Same as REG_IO_DDR_DRIVER:
+          # Register part of io_ddr_reg.vhd driver used in mms_io_ddr.vhd for write and read access to DDR memory via MM
           - - field_name: reg_burstbegin
               field_description: "Start write or read access to DDR when reg_burstbegin = 1."
               address_offset: 8 * MM_BUS_SIZE
@@ -65,5 +138,3 @@ peripherals:
                  The user input to the write FIFO should be off. Internally the method waits sufficient us to
                  ensure that the write FIFO is read empty."
               address_offset: 15 * MM_BUS_SIZE
-
-