Improve layout of entity IO.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -173,11 +173,12 @@ entity io_ddr is
     ctlr_ref_rst       : in    std_logic;
 
     -- DDR controller clock domain
+    -- . connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the
+    --   same clock. Connect ctlr_rst_out to ctlr_rst_in at top level.
     ctlr_clk_out       : out   std_logic;
     ctlr_rst_out       : out   std_logic;
-
-    ctlr_clk_in        : in    std_logic;  -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
-    ctlr_rst_in        : in    std_logic;  -- connect ctlr_rst_out to ctlr_rst_in at top level
+    ctlr_clk_in        : in    std_logic;
+    ctlr_rst_in        : in    std_logic;
 
     -- MM clock + reset
     mm_rst             : in    std_logic := '1';
@@ -191,14 +192,12 @@ entity io_ddr is
     -- Driver clock domain
     dvr_clk            : in    std_logic;
     dvr_rst            : in    std_logic;
-
     dvr_miso           : out   t_mem_ctlr_miso;
     dvr_mosi           : in    t_mem_ctlr_mosi;
 
     -- Write FIFO clock domain
     wr_clk             : in    std_logic;
     wr_rst             : in    std_logic;
-
     wr_fifo_usedw      : out   std_logic_vector(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / g_wr_data_w) ) - 1 downto 0);  -- for monitoring purposes
     wr_sosi            : in    t_dp_sosi;
     wr_siso            : out   t_dp_siso;
@@ -207,7 +206,6 @@ entity io_ddr is
     -- Read FIFO clock domain
     rd_clk             : in    std_logic;
     rd_rst             : in    std_logic;
-
     rd_fifo_usedw      : out   std_logic_vector(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / g_rd_data_w) ) - 1 downto 0);
     rd_sosi            : out   t_dp_sosi;
     rd_siso            : in    t_dp_siso;

libraries/io/ddr/src/vhdl/mms_io_ddr.vhd

@@ -48,11 +48,12 @@ entity mms_io_ddr is
     ctlr_ref_rst        : in    std_logic;
 
     -- DDR controller clock domain
+    -- . connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the
+    --   same clock. Connect ctlr_rst_out to ctlr_rst_in at top level.
     ctlr_clk_out        : out   std_logic;
     ctlr_rst_out        : out   std_logic;
-
-    ctlr_clk_in         : in    std_logic;  -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
-    ctlr_rst_in         : in    std_logic;  -- connect ctlr_rst_out to ctlr_rst_in at top level
+    ctlr_clk_in         : in    std_logic;
+    ctlr_rst_in         : in    std_logic;
 
     -- MM clock + reset
     mm_rst              : in    std_logic := '1';
@@ -65,7 +66,6 @@ entity mms_io_ddr is
     -- Write FIFO clock domain
     wr_clk              : in    std_logic;
     wr_rst              : in    std_logic;
-
     wr_fifo_usedw       : out   std_logic_vector(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / g_wr_data_w) ) - 1 downto 0);  -- for monitoring purposes
     wr_sosi             : in    t_dp_sosi;
     wr_siso             : out   t_dp_siso;
@@ -73,7 +73,6 @@ entity mms_io_ddr is
     -- Read FIFO clock domain
     rd_clk              : in    std_logic;
     rd_rst              : in    std_logic;
-
     rd_fifo_usedw       : out   std_logic_vector(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / g_rd_data_w) ) - 1 downto 0);
     rd_sosi             : out   t_dp_sosi;
     rd_siso             : in    t_dp_siso;