Ready for review.

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd

@@ -125,7 +125,7 @@ BEGIN
   q_reg <= d_reg WHEN rising_edge(clk);
 
   -- put the input data into c_v and fill the output vector from c_v
-  p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, dvr_miso, rd_fifo_usedw)
+  p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_ds, inp_bsn, inp_bsn_adr, dvr_miso, rd_fifo_usedw, stop_in)
 
     VARIABLE v                : t_reg         := c_t_reg_init;
 

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd

@@ -45,21 +45,30 @@ ENTITY ddrctrl_input_pack IS
 END ddrctrl_input_pack;
 
 ARCHITECTURE rtl OF ddrctrl_input_pack IS
-
 BEGIN
 
   -- Putting all the data from the different streams into one data vector.
   gen_extract_and_pack_data : FOR I IN 0 TO g_nof_streams-1 GENERATE
     p_generate : PROCESS(in_sosi_arr) IS
     BEGIN
-      IF in_sosi_arr(0).valid = '1' THEN
-        out_data(g_data_w*(I+1)-1 DOWNTO g_data_w*I) <= in_sosi_arr(I).data(g_data_w-1 DOWNTO 0);
-        out_valid <= '1';
-      ELSE
-        out_valid <= '0';
-      END IF;
+      out_data(g_data_w*(I+1)-1 DOWNTO g_data_w*I) <= in_sosi_arr(I).data(g_data_w-1 DOWNTO 0);
     END PROCESS;
   END GENERATE;
+
+
+  -- check if the input data is valid bij doing a and operation on all of them
+  p_valid : PROCESS(in_sosi_arr) IS
+
+    VARIABLE valid    : STD_LOGIC := '1';
+
+  BEGIN
+    valid := '1';
+    FOR I IN 0 TO g_nof_streams-1 LOOP
+      valid := valid AND in_sosi_arr(I).valid;
+    END LOOP;
+    out_valid <= valid;
+  END PROCESS;
+
   out_bsn <= in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
 
 END rtl;

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd

@@ -156,8 +156,8 @@ BEGIN
         fill_in_sosi_arr_0 : FOR I IN 0 TO g_nof_streams-1 LOOP
           in_sosi_arr(I).data(g_data_w-1 DOWNTO 0)   <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
           in_sosi_arr(I).valid <= '1';
+          in_sosi_arr(I).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
         END LOOP;
-        in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
         IF K = 1 AND J = 0 THEN
           stop_in <= '1';
         ELSE