From 6abd0eba22fda30f943d5be9c9f7df993a300e74 Mon Sep 17 00:00:00 2001
From: JobvanWee <wee@astron.nl>
Date: Tue, 12 Apr 2022 15:03:40 +0200
Subject: [PATCH] Ready for review.
---
.../ddrctrl/src/vhdl/ddrctrl_controller.vhd | 2 +-
.../ddrctrl/src/vhdl/ddrctrl_input_pack.vhd | 23 +++++++++++++------
.../libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd | 2 +-
3 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 8997d60756..d553823455 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -125,7 +125,7 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, dvr_miso, rd_fifo_usedw)
+ p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_ds, inp_bsn, inp_bsn_adr, dvr_miso, rd_fifo_usedw, stop_in)
VARIABLE v : t_reg := c_t_reg_init;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
index 1c2275bf33..8dfb6a752b 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
@@ -45,21 +45,30 @@ ENTITY ddrctrl_input_pack IS
END ddrctrl_input_pack;
ARCHITECTURE rtl OF ddrctrl_input_pack IS
-
BEGIN
-- Putting all the data from the different streams into one data vector.
gen_extract_and_pack_data : FOR I IN 0 TO g_nof_streams-1 GENERATE
p_generate : PROCESS(in_sosi_arr) IS
BEGIN
- IF in_sosi_arr(0).valid = '1' THEN
- out_data(g_data_w*(I+1)-1 DOWNTO g_data_w*I) <= in_sosi_arr(I).data(g_data_w-1 DOWNTO 0);
- out_valid <= '1';
- ELSE
- out_valid <= '0';
- END IF;
+ out_data(g_data_w*(I+1)-1 DOWNTO g_data_w*I) <= in_sosi_arr(I).data(g_data_w-1 DOWNTO 0);
END PROCESS;
END GENERATE;
+
+
+ -- check if the input data is valid bij doing a and operation on all of them
+ p_valid : PROCESS(in_sosi_arr) IS
+
+ VARIABLE valid : STD_LOGIC := '1';
+
+ BEGIN
+ valid := '1';
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ valid := valid AND in_sosi_arr(I).valid;
+ END LOOP;
+ out_valid <= valid;
+ END PROCESS;
+
out_bsn <= in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 7ac772d390..445f8d98fd 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -156,8 +156,8 @@ BEGIN
fill_in_sosi_arr_0 : FOR I IN 0 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
in_sosi_arr(I).valid <= '1';
+ in_sosi_arr(I).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
END LOOP;
- in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
IF K = 1 AND J = 0 THEN
stop_in <= '1';
ELSE
--
GitLab