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Commit 69e86d04 authored by Pepping's avatar Pepping
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Added pi_io_ddr object to check init done

parent f2af0b13
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...@@ -40,6 +40,7 @@ import pi_diag_block_gen ...@@ -40,6 +40,7 @@ import pi_diag_block_gen
import pi_diag_data_buffer import pi_diag_data_buffer
import pi_ss_ss_wide import pi_ss_ss_wide
import dsp_test import dsp_test
import pi_io_ddr
import sys, os import sys, os
import subprocess import subprocess
...@@ -114,6 +115,9 @@ db_im = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = 'IM', nofStr ...@@ -114,6 +115,9 @@ db_im = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = 'IM', nofStr
# Create subandselect instance for pre-transpose. # Create subandselect instance for pre-transpose.
ss = pi_ss_ss_wide.PiSsSsWide (tc, io, c_frame_size*g_rd_chunksize, c_nof_int_streams) ss = pi_ss_ss_wide.PiSsSsWide (tc, io, c_frame_size*g_rd_chunksize, c_nof_int_streams)
# Create object for DDR register map
ddr = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
# Create dsp_test instance for helpful methods # Create dsp_test instance for helpful methods
dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w) dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w)
...@@ -187,7 +191,7 @@ if __name__ == "__main__": ...@@ -187,7 +191,7 @@ if __name__ == "__main__":
# Wait until the DDR3 model is initialized. # Wait until the DDR3 model is initialized.
if tc.sim == True: if tc.sim == True:
do_until_gt(io.simIO.getSimTime, ms_retry=1000, val=110000, s_timeout=13600) # 110000 do_until_eq(ddr.read_init_done, ms_retry=1000, val=1, s_timeout=13600) # 110000
if(c_force_late_sync == 1): if(c_force_late_sync == 1):
if tc.sim == True: if tc.sim == True:
...@@ -299,3 +303,4 @@ if __name__ == "__main__": ...@@ -299,3 +303,4 @@ if __name__ == "__main__":
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