Merge branch 'L2SDP-400' into L2SDP-289

applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd

@@ -275,7 +275,8 @@ BEGIN
   GENERIC MAP (
     g_data_size          => c_data_size,
     g_step_size          => c_step_size,
-    g_nof_data  => c_nof_data
+    g_nof_data           => c_nof_data,
+    g_reverse_word_order => TRUE -- default word order is MSB after LSB, we need to stream LSB after MSB.
   ) 
   PORT MAP(
     dp_rst        => dp_rst,

libraries/base/dp/src/vhdl/dp_block_from_mm.vhd

@@ -18,7 +18,7 @@
 
 -- --------------------------------------------------------------------------
 -- Author: 
--- . Pieter Donker
+-- . Pieter Donker, R van der Walle
 -- Purpose:
 -- . Read a block of data from memory mapped (MM) location and stream it as a block of data.
 -- Description:
@@ -36,7 +36,8 @@ ENTITY dp_block_from_mm IS
   GENERIC (
     g_data_size          : NATURAL;
     g_step_size          : NATURAL;
-    g_nof_data   : NATURAL
+    g_nof_data           : NATURAL;
+    g_reverse_word_order : BOOLEAN := FALSE
   ); 
   PORT (
     rst           : IN  STD_LOGIC;
@@ -55,6 +56,7 @@ END dp_block_from_mm;
 ARCHITECTURE rtl OF dp_block_from_mm IS 
 
   CONSTANT c_mem_size : NATURAL := g_step_size * g_nof_data;
+  CONSTANT c_word_index_rst : NATURAL := sel_a_b(g_reverse_word_order, g_data_size - 1, 0);
 
   TYPE t_reg IS RECORD
     busy       : STD_LOGIC;
@@ -64,7 +66,7 @@ ARCHITECTURE rtl OF dp_block_from_mm IS
     step_index : NATURAL;
   END RECORD;
 
-  CONSTANT c_reg_rst : t_reg := ('0', '0', '0', 0, 0);
+  CONSTANT c_reg_rst : t_reg := ('0', '0', '0', c_word_index_rst, 0);
 
   SIGNAL r     : t_reg;
   SIGNAL nxt_r : t_reg;
@@ -111,6 +113,23 @@ BEGIN
       IF out_siso.ready = '1' THEN
         -- continue with block
         mm_mosi.rd <= '1';
+
+        IF g_reverse_word_order THEN
+
+          IF r.word_index > 0 THEN
+            v.word_index := r.word_index - 1;
+          ELSE
+            v.word_index := g_data_size - 1;
+            v.step_index := r.step_index + g_step_size;
+          END IF;
+          
+          -- check start of block
+          IF r.word_index = g_data_size - 1 AND r.step_index = 0 THEN
+            v.sop := '1';
+          END IF;
+
+        ELSE
+
           IF r.word_index < g_data_size - 1 THEN
             v.word_index := r.word_index + 1;
           ELSE
@@ -123,13 +142,23 @@ BEGIN
             v.sop := '1';
           END IF;
 
+        END IF;
+        
         -- check end of block
-        IF mm_address >= last_mm_address THEN
+        IF g_reverse_word_order THEN
+          IF mm_address = last_mm_address - (g_data_size - 1) THEN -- with reversed word order the last word to read is actually the first word of the last step index
+            v.eop := '1';
+            -- prepare for next block
+            v.busy := '0';
+            v.step_index := 0;
+            v.word_index := g_data_size - 1;
+          END IF;
+        ELSIF mm_address >= last_mm_address THEN -- g_reverse_word_order = False
           v.eop := '1';
           -- prepare for next block
           v.busy := '0';
-          v.word_index := 0;
           v.step_index := 0;
+          v.word_index := 0;
         END IF;
       END IF;
     END IF;

libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd

@@ -37,7 +37,8 @@ ENTITY dp_block_from_mm_dc IS
   GENERIC (
     g_data_size          : NATURAL;
     g_step_size          : NATURAL;
-    g_nof_data   : NATURAL
+    g_nof_data           : NATURAL;
+    g_reverse_word_order : BOOLEAN := FALSE
   ); 
   PORT (
     -- mm_clk domain
@@ -127,7 +128,8 @@ BEGIN
   GENERIC MAP (
     g_data_size          => g_data_size,
     g_step_size          => g_step_size,
-    g_nof_data  => g_nof_data 
+    g_nof_data           => g_nof_data,
+    g_reverse_word_order => g_reverse_word_order 
   )
   PORT MAP (
     clk         => mm_clk,

libraries/base/dp/src/vhdl/dp_sync_recover.vhd

@@ -95,7 +95,7 @@ BEGIN
     END IF;
   END PROCESS;  
 
-  p_comb : PROCESS(r, in_sosi, recover_val)
+  p_comb : PROCESS(r, in_sosi, recover_val, restart)
     VARIABLE v : t_reg;
   BEGIN
     v := r;