Added tb for xst offload and added mm interfaces

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg

@@ -9,9 +9,11 @@ hdl_lib_technology = ip_arria10_e1sg
 
 test_bench_files = 
     tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+    tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
 
 regression_test_vhdl =
     tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+    tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
 
 
 [modelsim_project_file]

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_xsub_one capturing BST UDP offload packets.
+--
+-- Description:
+--   MM control actions:
+--
+--   1) Enable BSN source and enable BST offload
+--   
+--   2) Verify ethernet statistics using eth_statistics, it checks the number of 
+--      received packets and the total number of valid data. The content of the packets is not verified.   
+--
+-- Usage:
+--   > as 7    # default
+--   > as 12   # for detailed debugging
+--   > run -a  
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS
+END tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; 
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period      : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period      : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+
+  CONSTANT c_tb_clk_period       : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+  CONSTANT c_nof_block_per_sync  : NATURAL := 16; -- long enough to stream out udp data
+  CONSTANT c_nof_clk_per_sync    : NATURAL := c_nof_block_per_sync*c_sdp_N_fft; 
+  CONSTANT c_pps_period          : NATURAL := c_nof_clk_per_sync;
+  CONSTANT c_wpfb_sim            : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+
+  -- MM  
+  CONSTANT c_mm_file_reg_bsn_source_v2     : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+  CONSTANT c_mm_file_reg_stat_enable_xst   : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST";
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+  SIGNAL tb_clk              : STD_LOGIC := '0';  
+  SIGNAL rd_data             : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL eth_done            : STD_LOGIC := '0';
+
+  -- . 1GbE output
+  CONSTANT c_eth_check_nof_packets        : NATURAL := 1; -- received packets in 1 sync period
+  CONSTANT c_eth_header_size              : NATURAL := 19; -- words
+  CONSTANT c_eth_crc_size                 : NATURAL := 1; -- word
+  CONSTANT c_eth_packet_size              : NATURAL := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_pn * c_sdp_S_pn; -- 20 + 2 * 12 * 12 = 308 
+  CONSTANT c_eth_check_nof_valid          : NATURAL := c_eth_check_nof_packets * c_eth_packet_size;  
+  CONSTANT c_eth_runtime_timeout          : TIME := 2 * c_nof_clk_per_sync * c_ext_clk_period;  -- eth statistics should be done at the second sync interval
+  
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL ext_pps             : STD_LOGIC := '0'; 
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL JESD204B_REFCLK      : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync_n     : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+  ext_pps <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_sdp_station_xsub_one : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+  GENERIC MAP (
+    g_design_name            => "lofar2_unb2b_sdp_station_xsub_one",
+    g_design_note            => "",
+    g_sim                    => c_sim,
+    g_sim_unb_nr             => c_unb_nr,
+    g_sim_node_nr            => c_node_nr,
+    g_wpfb                   => c_wpfb_sim,
+    g_bsn_nof_clk_per_sync   => c_nof_clk_per_sync
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- LEDs
+    QSFP_LED     => open,
+
+    -- back transceivers
+    JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+    JESD204B_REFCLK      => JESD204B_REFCLK,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC_N => jesd204b_sync_n
+  );
+
+  ------------------------------------------------------------------------------
+  -- MM slave accesses via file IO
+  ------------------------------------------------------------------------------
+  tb_clk  <= NOT tb_clk AFTER c_tb_clk_period/2;    -- Testbench MM clock
+  
+  p_mm_stimuli : PROCESS
+  BEGIN
+    -- Wait for DUT power up after reset
+    WAIT FOR 1 us;
+ 
+    ----------------------------------------------------------------------------
+    -- Enable BSN
+    ----------------------------------------------------------------------------
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3,                    0, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2,                    0, tb_clk);  -- Init BSN = 0
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1,   c_nof_clk_per_sync, tb_clk);  -- nof_block_per_sync
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0,         16#00000001#, tb_clk);  -- Enable BSN immediately 
+    
+    ----------------------------------------------------------------------------
+    -- Offload enable
+    ----------------------------------------------------------------------------
+    mmf_mm_bus_wr(c_mm_file_reg_stat_enable_xst_0, 0, 1, tb_clk);
+
+    -- wait for udp offload is done
+    proc_common_wait_until_high(ext_clk, eth_done);
+
+    ---------------------------------------------------------------------------
+    -- End Simulation 
+    ---------------------------------------------------------------------------  
+    sim_done <= '1';
+    proc_common_wait_some_cycles(ext_clk, 100);
+    proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+    WAIT;
+  END PROCESS;
+
+  -------------------------------------------------------------------------
+  -- Verify proper DUT 1GbE offload output using Ethernet packet statistics 
+  -------------------------------------------------------------------------
+  u_eth_statistics : ENTITY eth_lib.eth_statistics
+    GENERIC MAP (
+      g_runtime_nof_packets => c_eth_check_nof_packets,
+      g_runtime_timeout     => c_eth_runtime_timeout,
+      g_check_nof_valid     => TRUE,
+      g_check_nof_valid_ref => c_eth_check_nof_valid
+   )
+  PORT MAP (  
+    eth_serial_in => eth_txp(0),
+    tb_end        => eth_done
+  );
+
+END tb;

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd

@@ -362,6 +362,18 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
   -- Statistics header info  
   SIGNAL reg_stat_hdr_dat_sst_mosi      : t_mem_mosi;
   SIGNAL reg_stat_hdr_dat_sst_miso      : t_mem_miso;
+
+  ----------------------------------------------
+  -- XST 
+  ----------------------------------------------
+  -- Statistics Enable
+  SIGNAL reg_stat_enable_xst_mosi       : t_mem_mosi;
+  SIGNAL reg_stat_enable_xst_miso       : t_mem_miso;
+  
+  -- Statistics header info  
+  SIGNAL reg_stat_hdr_dat_xst_mosi      : t_mem_mosi;
+  SIGNAL reg_stat_hdr_dat_xst_miso      : t_mem_miso;
+
   ----------------------------------------------
   -- BST 
   ----------------------------------------------
@@ -693,6 +705,10 @@ BEGIN
     reg_stat_enable_sst_miso    => reg_stat_enable_sst_miso,
     reg_stat_hdr_dat_sst_mosi   => reg_stat_hdr_dat_sst_mosi,
     reg_stat_hdr_dat_sst_miso   => reg_stat_hdr_dat_sst_miso,
+    reg_stat_enable_xst_mosi    => reg_stat_enable_xst_mosi,
+    reg_stat_enable_xst_miso    => reg_stat_enable_xst_miso,
+    reg_stat_hdr_dat_xst_mosi   => reg_stat_hdr_dat_xst_mosi,
+    reg_stat_hdr_dat_xst_miso   => reg_stat_hdr_dat_xst_miso,
     reg_stat_enable_bst_mosi    => reg_stat_enable_bst_mosi,
     reg_stat_enable_bst_miso    => reg_stat_enable_bst_miso,
     reg_stat_hdr_dat_bst_mosi   => reg_stat_hdr_dat_bst_mosi,

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd

@@ -190,6 +190,14 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
    reg_stat_hdr_dat_sst_mosi      : OUT t_mem_mosi;
    reg_stat_hdr_dat_sst_miso      : IN  t_mem_miso;
 
+   -- Crosslet Statistics offload
+   reg_stat_enable_xst_mosi       : OUT t_mem_mosi;
+   reg_stat_enable_xst_miso       : IN  t_mem_miso;
+
+   -- Crosslet Statistics header info
+   reg_stat_hdr_dat_xst_mosi      : OUT t_mem_mosi;
+   reg_stat_hdr_dat_xst_miso      : IN  t_mem_miso;
+
    -- Beamlet Statistics offload 
    reg_stat_enable_bst_mosi       : OUT t_mem_mosi;
    reg_stat_enable_bst_miso       : IN  t_mem_miso;
@@ -344,6 +352,12 @@ BEGIN
 
     u_mm_file_reg_stat_hdr_info_sst   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
                                                 PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_mosi, reg_stat_hdr_dat_sst_miso);
+    
+    u_mm_file_reg_stat_enable_xst     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
+                                                PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_mosi, reg_stat_enable_xst_miso );
+
+    u_mm_file_reg_stat_hdr_info_xst   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
+                                                PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_mosi, reg_stat_hdr_dat_xst_miso);
 
     u_mm_file_reg_stat_enable_bst     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
                                                 PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_mosi, reg_stat_enable_bst_miso );
@@ -731,6 +745,22 @@ BEGIN
       reg_stat_hdr_dat_sst_read_export          => reg_stat_hdr_dat_sst_mosi.rd,
       reg_stat_hdr_dat_sst_readdata_export      => reg_stat_hdr_dat_sst_miso.rddata(c_word_w-1 DOWNTO 0),
 
+      reg_stat_enable_xst_clk_export            => OPEN,
+      reg_stat_enable_xst_reset_export          => OPEN,
+      reg_stat_enable_xst_address_export        => reg_stat_enable_xst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+      reg_stat_enable_xst_write_export          => reg_stat_enable_xst_mosi.wr,
+      reg_stat_enable_xst_writedata_export      => reg_stat_enable_xst_mosi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_stat_enable_xst_read_export           => reg_stat_enable_xst_mosi.rd,
+      reg_stat_enable_xst_readdata_export       => reg_stat_enable_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_stat_hdr_dat_xst_clk_export           => OPEN,
+      reg_stat_hdr_dat_xst_reset_export         => OPEN,
+      reg_stat_hdr_dat_xst_address_export       => reg_stat_hdr_dat_xst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+      reg_stat_hdr_dat_xst_write_export         => reg_stat_hdr_dat_xst_mosi.wr,
+      reg_stat_hdr_dat_xst_writedata_export     => reg_stat_hdr_dat_xst_mosi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_stat_hdr_dat_xst_read_export          => reg_stat_hdr_dat_xst_mosi.rd,
+      reg_stat_hdr_dat_xst_readdata_export      => reg_stat_hdr_dat_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+
       reg_stat_enable_bst_clk_export            => OPEN,
       reg_stat_enable_bst_reset_export          => OPEN,
       reg_stat_enable_bst_address_export        => reg_stat_enable_bst_mosi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd

@@ -301,6 +301,20 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
             reg_stat_hdr_dat_sst_reset_export         : out std_logic;                                        -- export
             reg_stat_hdr_dat_sst_write_export         : out std_logic;                                        -- export
             reg_stat_hdr_dat_sst_writedata_export     : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_enable_xst_address_export        : out std_logic_vector(0 downto 0);                     -- export
+            reg_stat_enable_xst_clk_export            : out std_logic;                                        -- export
+            reg_stat_enable_xst_read_export           : out std_logic;                                        -- export
+            reg_stat_enable_xst_readdata_export       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_enable_xst_reset_export          : out std_logic;                                        -- export
+            reg_stat_enable_xst_write_export          : out std_logic;                                        -- export
+            reg_stat_enable_xst_writedata_export      : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_hdr_dat_xst_address_export       : out std_logic_vector(5 downto 0);                     -- export
+            reg_stat_hdr_dat_xst_clk_export           : out std_logic;                                        -- export
+            reg_stat_hdr_dat_xst_read_export          : out std_logic;                                        -- export
+            reg_stat_hdr_dat_xst_readdata_export      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_hdr_dat_xst_reset_export         : out std_logic;                                        -- export
+            reg_stat_hdr_dat_xst_write_export         : out std_logic;                                        -- export
+            reg_stat_hdr_dat_xst_writedata_export     : out std_logic_vector(31 downto 0);                    -- export
             reg_stat_enable_bst_address_export        : out std_logic_vector(1 downto 0);                     -- export
             reg_stat_enable_bst_clk_export            : out std_logic;                                        -- export
             reg_stat_enable_bst_read_export           : out std_logic;                                        -- export

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd

@@ -62,10 +62,10 @@ ENTITY node_sdp_correlator IS
     reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
     ram_st_xsq_mosi             : IN  t_mem_mosi := c_mem_mosi_rst;
     ram_st_xsq_miso             : OUT t_mem_miso;
-    reg_enable_mosi             : IN  t_mem_mosi := c_mem_mosi_rst;
-    reg_enable_miso             : OUT t_mem_miso;    
-    reg_hdr_dat_mosi            : IN  t_mem_mosi := c_mem_mosi_rst;
-    reg_hdr_dat_miso            : OUT t_mem_miso;
+    reg_stat_enable_mosi        : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_stat_enable_miso        : OUT t_mem_miso;    
+    reg_stat_hdr_dat_mosi       : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_stat_hdr_dat_miso       : OUT t_mem_miso;
 
     sdp_info : IN t_sdp_info;
     gn_id    : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);