-Set g_use_bg to TRUE;

-Commented out SI_FN pins in TCL file;
-Updated tc_apertif_unb1_correlator_offload.py to be aware of channel indices.

applications/apertif/designs/apertif_unb1_correlator/quartus/apertif_unb1_correlator_pins.tcl

@@ -23,5 +23,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
-source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs.tcl
+#source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs.tcl
 #source $::env(UNB)/Firmware/designs/unb_common/src/tcl/FRONT_NODE_mesh_nocmu_pins.tcl

applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd

@@ -62,7 +62,7 @@ USE bf_lib.bf_pkg.ALL;
 ENTITY apertif_unb1_correlator IS
   GENERIC (
     g_design_name             : STRING  := "apertif_unb1_correlator";
-    g_use_bg                  : BOOLEAN := FALSE; -- Overridden (TRUE) by TB but still a valid synthesis option; this replaces the 10GbE input stage with block gens.
+    g_use_bg                  : BOOLEAN := TRUE; -- Overridden (TRUE) by TB but still a valid synthesis option; this replaces the 10GbE input stage with block gens.
     g_sim                     : BOOLEAN := FALSE; -- Overridden by TB
     g_sim_fast                : BOOLEAN := TRUE; -- TRUE = fast accumulator model and no inter-channel delay in the correlator output stream.
     g_sim_unb_nr              : NATURAL := 0;

applications/apertif/designs/apertif_unb1_correlator/tb/python/tc_apertif_unb1_correlator_offload.py

@@ -52,6 +52,9 @@ def dumpfile_to_array(dumpfile):
     # Strip off the PCAP header
     pcap_global_hdr_raw = f.read(24)
 
+    # Examine packets but don't append to return list until after channel 0 is found
+    append_channels = False
+
     for packet in range(960): # 960 channels = 15 integration periods of 64 channels.
         pcap_pkt_hdr_raw = f.read(16)
         eth_hdr_raw = f.read(14)
@@ -125,6 +128,9 @@ def dumpfile_to_array(dumpfile):
         print 'Packet', packet, '-', 'id_reserved                 ', id_hdr_bits[79:64]
         print 'Packet', packet, '-', 'id_timestamp                ', id_hdr_bits[63:0]
 
+        channel = id_hdr_bits[95:80]
+        timestamp = id_hdr_bits[63:0]
+
         ###########################################################################
         # Flag header: 24 big endian bytes = 192 bits
         ###########################################################################
@@ -160,6 +166,11 @@ def dumpfile_to_array(dumpfile):
         for i,v in enumerate(visibilities_complex):
             print 'Packet', packet, '-', 'Visibility %03d              ' %i, v
 
+        # Tag the moment we've found channel 0.
+        if channel==0:
+            append_channels = True
+
+        if append_channels == True:
             channel_visibilities.append(visibilities_complex)
 
     # Return our list [NOF_CHANNELS][NOF_VISIBILITIES]