Avoid using same address for wr_adr_b as for wr_adr_a.

libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd

@@ -19,6 +19,7 @@
 --
 -------------------------------------------------------------------------------
 
+-- Author: E. Kooistra
 -- Purpose: Dual page memory with single wr in one page and dual rd in other page
 -- Description:
 --   When next_page pulses then the next access will occur in the other page.
@@ -63,7 +64,19 @@ entity common_paged_ram_w_rr is
 end common_paged_ram_w_rr;
 
 architecture str of common_paged_ram_w_rr is
+  signal wr_adr_b : std_logic_vector(wr_adr'range);
 begin
+  -- Make used wr_adr_b for page b always differ from wr_adr for port a, to avoid read and write at same address,
+  -- which would yield undefined data result in simulation (and maybe also on HW even though wr_en_b = '0') when
+  -- block RAM mixed_port_feed_through_mode = DONT_CARE.
+  p_wr_adr_b : process(wr_adr)
+  begin
+    wr_adr_b <= (others => '0');
+    if to_uint(wr_adr) = 0 then
+      wr_adr_b(0) <= '1';
+    end if;
+  end process;
+
   u_ww_rr : entity work.common_paged_ram_ww_rr
   generic map (
     g_technology     => g_technology,
@@ -83,6 +96,7 @@ begin
     wr_adr_a    => wr_adr,
     wr_en_a     => wr_en,
     wr_dat_a    => wr_dat,
+    wr_adr_b    => wr_adr_b,
     -- double read access from the other one page
     rd_adr_a    => rd_adr_a,
     rd_en_a     => rd_en_a,

libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd

@@ -38,7 +38,10 @@ begin
   --   g_pipeline_out    : NATURAL := 0;   -- >= 0
   --   g_page_sz         : NATURAL := 10   -- >= 1
 
-  u_1             : entity work.tb_common_paged_ram_ww_rr generic map (0, 0, 1);
+  -- Cannot support g_page_sz = 1, when block RAM mixed_port_feed_through_mode = DONT_CARE, because with only one
+  -- word the adr_a cannot be different from adr_b. Using g_page_sz = 1 is an extreme corner case, because the
+  -- RAM only has one word, so acts as a register.
+  --u_1             : entity work.tb_common_paged_ram_ww_rr generic map (0, 0, 1);
   u_2             : entity work.tb_common_paged_ram_ww_rr generic map (0, 0, 2);
   u_8             : entity work.tb_common_paged_ram_ww_rr generic map (0, 0, 8);