Use read_during_write_mode_mixed_ports = DONT_CARE

libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd

@@ -53,6 +53,8 @@ end ip_arria10_e2sg_ram_cr_cw;
 architecture SYN of ip_arria10_e2sg_ram_cr_cw is
   constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
 
+  -- Either comment read_during_write_mode_mixed_ports generic in component and instance, or uncomment both and
+  -- assign default "DONT_CARE" at instance.
   component altera_syncram
   generic (
           address_aclr_b  : string;
@@ -69,7 +71,7 @@ architecture SYN of ip_arria10_e2sg_ram_cr_cw is
           outdata_aclr_b  : string;
           outdata_reg_b  : string;
           power_up_uninitialized  : string;
-          read_during_write_mode_mixed_ports : string;  -- use default DONT_CARE
+          --read_during_write_mode_mixed_ports : string;  -- use default DONT_CARE
           widthad_a  : integer;
           widthad_b  : integer;
           width_a  : integer;
@@ -115,6 +117,7 @@ begin
             outdata_aclr_b  => "NONE",
             outdata_reg_b  => c_outdata_reg_b,
             power_up_uninitialized  => "FALSE",
+            --read_during_write_mode_mixed_ports => "DONT_CARE",
             widthad_a  => g_adr_w,
             widthad_b  => g_adr_w,
             width_a  => g_dat_w,

libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd

@@ -57,6 +57,8 @@ architecture SYN of ip_arria10_e2sg_ram_crw_crw is
   constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
   constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
 
+  -- Either comment read_during_write_mode_mixed_ports generic in component and instance, or uncomment both and
+  -- assign default "DONT_CARE" at instance.
   component altera_syncram
   generic (
           address_reg_b  : string;
@@ -78,7 +80,7 @@ architecture SYN of ip_arria10_e2sg_ram_crw_crw is
           power_up_uninitialized  : string;
           read_during_write_mode_port_a  : string;
           read_during_write_mode_port_b  : string;
-          read_during_write_mode_mixed_ports : string;  -- use default DONT_CARE
+          --read_during_write_mode_mixed_ports : string;  -- use default DONT_CARE
           widthad_a  : integer;
           widthad_b  : integer;
           width_a  : integer;
@@ -136,6 +138,7 @@ begin
             power_up_uninitialized  => "FALSE",
             read_during_write_mode_port_a  => "NEW_DATA_NO_NBE_READ",
             read_during_write_mode_port_b  => "NEW_DATA_NO_NBE_READ",
+            --read_during_write_mode_mixed_ports => "DONT_CARE",
             widthad_a  => g_adr_w,
             widthad_b  => g_adr_w,
             width_a  => g_dat_w,

libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd

@@ -47,6 +47,8 @@ architecture SYN of ip_arria10_e2sg_ram_crwk_crw is
   constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
   constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
 
+  -- Either omit or comment read_during_write_mode_mixed_ports generic in component and instance, or declare generic
+  -- and assign default "DONT_CARE" at instance.
   component altera_syncram
   generic (
           address_reg_b  : string;

libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd

@@ -51,6 +51,8 @@ end ip_arria10_e2sg_ram_r_w;
 architecture SYN of ip_arria10_e2sg_ram_r_w is
   constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
 
+  -- Either omit or comment read_during_write_mode_mixed_ports generic in component and instance, or declare generic
+  -- and assign default "DONT_CARE" at instance.
   component altera_syncram
   generic (
           address_aclr_b  : string;