areset -> async

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd

@@ -368,15 +368,15 @@ BEGIN
 
       rx_xcvr_ready_in_arr(i) <= '1' when  rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
       -- synchronize rx_xcvr_ready_in_arr to mm_clk
-      u_common_areset_rx_xcvr_ready : ENTITY common_lib.common_areset
+      u_common_async_rx_xcvr_ready : ENTITY common_lib.common_async
       GENERIC MAP (
-        g_in_rst_level => '0', -- rst is asserted immediately in_rst = '0'
-        g_rst_level    => '0'  -- When in_rst is asserted, out_rst = '0'
+        g_rst_level => '0'  -- When in_rst is asserted, dout = '0'
       )
       PORT MAP (
-        in_rst  => rx_xcvr_ready_in_arr(i),
-        clk     => mm_clk,
-        out_rst => mm_rx_xcvr_ready_in_arr(i)
+        rst  => mm_rst,
+        clk  => mm_clk,
+        din  => rx_xcvr_ready_in_arr(i),
+        dout => mm_rx_xcvr_ready_in_arr(i)
       ); 
 
       -- Invert thr active-low resets

libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd

@@ -367,15 +367,15 @@ BEGIN
 
       rx_xcvr_ready_in_arr(i) <= '1' when  rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
       -- synchronize rx_xcvr_ready_in_arr to mm_clk
-      u_common_areset_rx_xcvr_ready : ENTITY common_lib.common_areset
+      u_common_async_rx_xcvr_ready : ENTITY common_lib.common_async
       GENERIC MAP (
-        g_in_rst_level => '0', -- rst is asserted immediately in_rst = '0'
-        g_rst_level    => '0'  -- When in_rst is asserted, out_rst = '0'
+        g_rst_level => '0'  -- When in_rst is asserted, dout = '0'
       )
       PORT MAP (
-        in_rst  => rx_xcvr_ready_in_arr(i),
-        clk     => mm_clk,
-        out_rst => mm_rx_xcvr_ready_in_arr(i)
+        rst  => mm_rst,
+        clk  => mm_clk,
+        din  => rx_xcvr_ready_in_arr(i),
+        dout => mm_rx_xcvr_ready_in_arr(i)
       ); 
 
       -- Invert thr active-low resets