-Completed sensitivity list.

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd

@@ -151,7 +151,7 @@ BEGIN
     -- The pipeline_ready module is needed to alleviate timing errors
     -----------------------------------------------------------------------------
 
-    p_overide_empty : PROCESS(dp_counter_data_src_out_arr(tabno))
+    p_overide_empty : PROCESS(dp_counter_data_src_out_arr(tabno), dp_counter_count_src_out_arr)
     BEGIN
       dp_repack_snk_in_arr(tabno)       <= dp_counter_data_src_out_arr(tabno);
       dp_repack_snk_in_arr(tabno).sop   <= dp_counter_count_src_out_arr(0).sop;