From 6396f7cf0f46f5dd489efeff50de25ba5031be6b Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Fri, 27 Jul 2018 07:45:32 +0000
Subject: [PATCH] -Completed sensitivity list.
---
.../src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
index 9dc66746bb..a22724d868 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
@@ -151,7 +151,7 @@ BEGIN
-- The pipeline_ready module is needed to alleviate timing errors
-----------------------------------------------------------------------------
- p_overide_empty : PROCESS(dp_counter_data_src_out_arr(tabno))
+ p_overide_empty : PROCESS(dp_counter_data_src_out_arr(tabno), dp_counter_count_src_out_arr)
BEGIN
dp_repack_snk_in_arr(tabno) <= dp_counter_data_src_out_arr(tabno);
dp_repack_snk_in_arr(tabno).sop <= dp_counter_count_src_out_arr(0).sop;
--
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