Corrections for merge

applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd

@@ -440,7 +440,7 @@ BEGIN
 
       ram_diag_data_buf_bsn_clk_export          => OPEN,
       ram_diag_data_buf_bsn_reset_export        => OPEN,
-      ram_diag_data_buf_bsn_address_export      => ram_diag_data_buf_bsn_mosi.address(21-1 DOWNTO 0),
+      ram_diag_data_buf_bsn_address_export      => ram_diag_data_buf_bsn_mosi.address(21-1 DOWNTO 0), -- 22 = ceil_log2(12  * 256k), so maximum possible data buffer size is 256 kSamples
       ram_diag_data_buf_bsn_write_export        => ram_diag_data_buf_bsn_mosi.wr,
       ram_diag_data_buf_bsn_writedata_export    => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
       ram_diag_data_buf_bsn_read_export         => ram_diag_data_buf_bsn_mosi.rd,

libraries/technology/jesd204b/tb_tech_jesd204b.vhd

@@ -49,6 +49,7 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
   CONSTANT c_jesd204b_sampclk_period  : TIME := 5 ns;
   CONSTANT c_bondingclk_period        : TIME := 10 ns;
   CONSTANT c_sysref_period            : NATURAL := 10000; -- number of sample clocks between sysref pulses
+  CONSTANT c_sysref_pulselength       : NATURAL := 7;     -- number of sample clocks that sysref is high (>= 1)
 
   CONSTANT c_nof_jesd204b_tx          : NATURAL := 3;  -- number of jesd204b input sources to instantiate
   CONSTANT c_nof_streams_jesd204b     : NATURAL := 12; -- number of jesd204b receiver channels
@@ -165,7 +166,7 @@ BEGIN
   GENERIC MAP(
     g_sim                => c_sim,                
     g_nof_streams        => c_nof_streams_jesd204b,
-    g_nof_sync_n         => c_nof_streams_jesd204b        -- Todo: Try three ADCs per RCU share a sync
+    g_nof_sync_n         => c_nof_streams_jesd204b        
   )
   PORT MAP(
     jesd204b_refclk      => jesd204b_sampclk_fpga,   
@@ -280,6 +281,8 @@ BEGIN
            txlink_clk(i) <= not txlink_clk(i);
            jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
            jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+
+           --generate a positive and negative going pulse after the rising edge of SYSREF
            IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
              data := 1000;
            ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
@@ -322,6 +325,12 @@ BEGIN
   txlink_rst_n <= '0', '1' after 25500 ns;
   pll_locked(0) <= '0', '1' after 1000 ns;
   
+
+  -- Create bonding clocks
+  -- The clock periods and offsets are copied from the JESD TX sample design
+  -- They are created directly to simplifiy the test bench
+  -- bonding_clock_1 has an uneven duty cycle
+
   bonding_clock_5 <= not bonding_clock_5 after 250 ps;
   bonding_clock_4 <= not bonding_clock_4 after 250 ps;
   bonding_clock_3 <= not bonding_clock_3 after 500 ps;
@@ -345,7 +354,7 @@ BEGIN
 		     
   
   -- clock source process
-
+  -- generate the sysref pulses
   proc_sysref : PROCESS (jesd204b_sampclk, mm_rst)
     VARIABLE count  : NATURAL := 0;
   BEGIN
@@ -360,7 +369,7 @@ BEGIN
            count := count + 1;
          END IF;
          
-         IF count > c_sysref_period-8 THEN
+         IF count > c_sysref_period-1-c_sysref_pulselength THEN
            jesd204b_sysref <= '1';
          ELSE
            jesd204b_sysref <= '0';
@@ -371,6 +380,9 @@ BEGIN
 
   ------------------------------------------------------------------------------
   -- Diagnostics
+  -- Read registers in the tx jesd core to check it comes out of reset Ok
+  -- The meaning of specific register bits is defined in section 4.7.2 of the User Guide
+  -- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
   ------------------------------------------------------------------------------
   proc_read_avs_regs : PROCESS
   BEGIN
@@ -448,7 +460,7 @@ BEGIN
   ------------------------------------------------------------------------------
   -- Simulation end
   ------------------------------------------------------------------------------
-  --sim_done <= '0', '1' AFTER 1 us;
+
   sim_done <=   '1' when rx_sosi_arr(0).valid = '1' and rx_sosi_arr(1).valid = '1' and rx_sosi_arr(2).valid = '1' else '0';
   tb_end <= '0', '1' after 110 us;