self stopping self checking test bench for tech_jesd204b.
Closes L2SDP-86
Test bench tb_tech_jesd204b is now self checking and self stopping. I have added it to the regression test.
Also includes adding second eth1g port to unb2c pinning design, and modifications needed to increase lofar2_unb2b_adc_full buffer size to 128k.
Merge request reports
Activity
228 228 reg_aduh_monitor_reset_export : out std_logic; -- export 229 229 reg_aduh_monitor_write_export : out std_logic; -- export 230 230 reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export 231 ram_diag_data_buf_bsn_address_export : out std_logic_vector(15 downto 0); -- export -
I now think there are data_buffer_jesd (close to IP) and data_buffer_bsn (at node ait output) right? Then data_buffer_bsn name is fine.
Edited by Eric Kooistra -
Yes best leave it as it is, the name is fine. I have made L2SDP-164 for a later sprint.
448 449 -- Simulation end 449 450 ------------------------------------------------------------------------------ 450 451 --sim_done <= '0', '1' AFTER 1 us; 451 sim_done <= '0'; -
There is no passed / failed check, is there? There should be some check that e.g. valid data comes out of the Rx JESD (e.g. in proc_data?)
Edited by Eric Kooistra
371 372 ------------------------------------------------------------------------------ 372 373 -- Diagnostics 373 374 ------------------------------------------------------------------------------ 374 375 proc_read_avs_regs : PROCESS 359 360 count := count + 1; 360 361 END IF; 361 362 362 363 IF count > c_sysref_period-8 THEN changed this line in version 2 of the diff
164 165 GENERIC MAP( 165 166 g_sim => c_sim, 166 167 g_nof_streams => c_nof_streams_jesd204b, 167 168 g_nof_sync_n => c_nof_streams_jesd204b -- Todo: Try three ADCs per RCU share a sync changed this line in version 2 of the diff
327 328 bonding_clock_2 <= not bonding_clock_2 after 500 ps; 328 329 bonding_clock_0 <= not bonding_clock_0 after 2500 ps; 329 330 330 331 bonding_clock_1_process : process -
Comment to explain why the bonding clocks are made like this. Why are there 6 tx bonding clocks and why are the delay values like they are. Why is bonding_clock_1 made differently.
Edited by Eric Kooistra
279 280 txlink_clk(i) <= not txlink_clk(i); 280 281 jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i); 281 282 jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i); 282 283 IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN 95 95 set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}] 96 96 set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}] 97 97 set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}] 98 99 # Constraint on the SYSREF input pin 100 # Adjust this to account for any board trace difference between SYSREF and REFCLK 101 set_input_delay -clock BCK_REF_CLK 0 [get_ports JESD204B_SYSREF] -
Question regarding the node_adc_input_and_timing design, does the synthesis work ok without severe warnings and timing violations on the jesd204b ?
Edited by Eric Kooistra
440 440 441 441 ram_diag_data_buf_bsn_clk_export => OPEN, 442 442 ram_diag_data_buf_bsn_reset_export => OPEN, 443 ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(16-1 DOWNTO 0), 443 ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21-1 DOWNTO 0), changed this line in version 2 of the diff
mentioned in commit 70c5bfc6
