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RTSD
HDL
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61e02d0f
Commit
61e02d0f
authored
4 years ago
by
Kenneth Hiemstra
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updated README
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b8b931a0
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boards/uniboard2b/designs/unb2b_minimal/doc/README
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61e02d0f
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@@ -7,6 +7,7 @@ On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
-> In case of a new installation, the IP's have to be generated for Arria10.
cd ~/git/hdl
. init_hdl.sh
compile_altera_simlibs unb2b
generate_ip_libs unb2b
-> For compilation it might be necessary to check the .vhd file:
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@@ -19,10 +20,10 @@ On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
1. Start with the Oneclick Commands:
cd ~/git/hdl
. init_hdl.sh
quartus_config
quartus_config
unb2b
# 2. Generate MMM for QSYS:
run_qsys unb2b unb2b_minimal
run_qsys
_pro
unb2b unb2b_minimal
3. -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
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