Added remark for reason why ip_agi027_xxxx_ram_rw_rw is added to...

Added remark for reason why ip_agi027_xxxx_ram_rw_rw is added to tech_memory_ram_crw_crw and to tech_memory_ram_crwk_crw.

libraries/technology/ip_agi027_xxxx/ram/README.txt

 README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/ram
-VERSION 01 - 20231110
+VERSION 02 - 20231218
 
 Contents:
 
@@ -11,7 +11,8 @@ Contents:
 6) Implementation options (LUTs or block RAM)
 7) Synthesis trials
 8) Agilex7 issues
-9) References
+9) Remarks
+10) References
 
 
 
@@ -32,6 +33,7 @@ Contents:
                                  Not available, because the Agilex 7 does not support ratio widths in combination with true dual port mode.
 
 
+
 2) ROM components:
    ip_agi027_xxxx_rom_r_w      = Not available and not needed, because the ip_agi027_xxxx_ram_r_w can be used for ROM IP by not connecting the
                                  write port. The IP could be created and than the vhd file can be derived from the generated HDL files and the
@@ -44,7 +46,7 @@ Contents:
   The RAM IPs were ported manually from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_xxxx by creating it in Quartus
   using the same parameter settings by:
 
-   - methode A:
+   - method A:
     . copy original ip_arria_e2sg_<ram_name>.vhd and ip_arria_e2sg_<ram_name>.ip files.
     . rename ip_arria_e2sg_<ram_name>.ip and .vhd into ip_agi027_xxxx_<ram_name>.ip and .vhd (also replace name inside the .vhd file)
     . open in to Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB. 
@@ -55,7 +57,7 @@ Contents:
       necessary to make it work.
     . git commit also the ip_agi027_xxxx_<ram_name>.ip to preserve the original in case it needs to be modified.
 
-   - methode B:
+   - method B:
     . copy original ip_arria_e2sg_<ram_name>.vhd file.
     . rename ip_arria_e2sg_<ram_name>.vhd into ip_agi027_xxxx_<ram_name>.vhd (also replace name inside the .vhd file).
     . open ip_arria_e2sg_<ram_name>.ip file in Quartus 19.4.0 build 64. No device family and device part need to be set.
@@ -235,7 +237,23 @@ Contents:
       as there is also no testbench for the underlying 'common_ram_crw_crw_ratio' file that was utilized.
 
 
-9) References:
+
+9)    Remarks:
+
+  a)  For tech_memory_ram_crw_crw the ip_agi027_xxxx_rw_rw is added, because in a lot of files at the higher layer common_ram_crw_crw.vhd is used.
+      It is not preferable to add an extra generic or the technology there, to generate the right used component.
+      So it is better to implement a clock domain cross component such as dp_fifo_dc_arr or common_reg_cross_domain (to save logic and/or RAM)
+      when needed at a design at the higher layer. A lot of designs cannot have an extra latency, and then one clock domain is also an option.
+  b)  For tech_memory_ram_crwk_crw the ip_agi027_xxxx_rw_rw is added, because the ip_agi027_xxxx_crk_cw has one read and one write port and 
+      the mm port should have read/write possibility to check if standard rewrite to '0'-values is going well by writing other values then '0'
+      before to mm domain. To keep this therefore a DC_FIFO in combination with a MUX need to be added. (Also it is possible to check this with mm reg.)
+      And because only one clock domain is used in the other designs by the Agilex 7, ram_rw_rw makes the most suitable solution. 
+      To have the ratio option is less important. That one can also be added with dp_repack if needed.
+      This results in: one clock domain and a fixed datarate.
+
+
+
+10) References:
 
   [1] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/true-dual-port-dual-clock-emulator.html
   [2] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/embedded-memory-configurations.html