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RTSD
HDL
Commits
602c454f
Commit
602c454f
authored
9 years ago
by
Reinier van der Walle
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libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
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602c454f
-------------------------------------------------------------------------------
--
-- Copyright (C) 2010
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose:
-- Test bench for mms_dp_fifo_fill
-- Description:
-- The tb creates a data stream and checks if the register can be readline
-- The value that is read via MM should be checked in the wave window.
--
-- Remark:
-- It is not possible to check if the wr_full bit is set. That is because of the
-- assert in de common_fifo_sc definition.
--
-- Usage:
-- > as 10
-- > run -all
-- . signal tb_end will stop the simulation by stopping the clk
--
LIBRARY
IEEE
,
common_lib
;
USE
IEEE
.
std_logic_1164
.
ALL
;
USE
IEEE
.
numeric_std
.
ALL
;
USE
common_lib
.
common_pkg
.
ALL
;
USE
common_lib
.
common_lfsr_sequences_pkg
.
ALL
;
USE
common_lib
.
tb_common_pkg
.
ALL
;
USE
common_lib
.
common_mem_pkg
.
ALL
;
USE
common_lib
.
tb_common_mem_pkg
.
ALL
;
USE
common_lib
.
common_field_pkg
.
ALL
;
USE
work
.
dp_stream_pkg
.
ALL
;
USE
work
.
tb_dp_pkg
.
ALL
;
ENTITY
tb_dp_offload_rx_filter
IS
END
tb_dp_offload_rx_filter
;
ARCHITECTURE
tb
OF
tb_dp_offload_rx_filter
IS
CONSTANT
c_nof_stream
:
NATURAL
:
=
1
;
CONSTANT
c_data_w
:
NATURAL
:
=
64
;
CONSTANT
c_correct_mac
:
STD_LOGIC_VECTOR
(
47
DOWNTO
0
)
:
=
x"FFABCDABCDFF"
;
CONSTANT
c_correct_ip
:
STD_LOGIC_VECTOR
(
31
DOWNTO
0
)
:
=
x"12345678"
;
CONSTANT
c_correct_length
:
NATURAL
:
=
50
;
CONSTANT
c_correct_port
:
NATURAL
:
=
4000
;
CONSTANT
c_wrong_mac
:
STD_LOGIC_VECTOR
(
47
DOWNTO
0
)
:
=
x"BBBBBBBBBBBB"
;
CONSTANT
c_wrong_ip
:
STD_LOGIC_VECTOR
(
31
DOWNTO
0
)
:
=
x"AAAAAAAA"
;
CONSTANT
c_wrong_length
:
NATURAL
:
=
60
;
CONSTANT
c_wrong_port
:
NATURAL
:
=
4001
;
CONSTANT
c_nof_packets
:
NATURAL
:
=
5
;
CONSTANT
c_nof_hdr_fields
:
NATURAL
:
=
3
+
12
+
4
+
9
+
1
;
CONSTANT
c_hdr_field_arr
:
t_common_field_arr
(
c_nof_hdr_fields
-1
DOWNTO
0
)
:
=
(
(
field_name_pad
(
"eth_dst_mac"
),
" "
,
48
,
field_default
(
0
)
),
(
field_name_pad
(
"eth_src_mac"
),
" "
,
48
,
field_default
(
0
)
),
(
field_name_pad
(
"eth_type"
),
" "
,
16
,
field_default
(
x"0800"
)
),
(
field_name_pad
(
"ip_version"
),
" "
,
4
,
field_default
(
4
)
),
(
field_name_pad
(
"ip_header_length"
),
" "
,
4
,
field_default
(
5
)
),
(
field_name_pad
(
"ip_services"
),
" "
,
8
,
field_default
(
0
)
),
(
field_name_pad
(
"ip_total_length"
),
" "
,
16
,
field_default
(
0
)
),
(
field_name_pad
(
"ip_identification"
),
" "
,
16
,
field_default
(
0
)
),
(
field_name_pad
(
"ip_flags"
),
" "
,
3
,
field_default
(
2
)
),
(
field_name_pad
(
"ip_fragment_offset"
),
" "
,
13
,
field_default
(
0
)
),
(
field_name_pad
(
"ip_time_to_live"
),
" "
,
8
,
field_default
(
127
)
),
(
field_name_pad
(
"ip_protocol"
),
" "
,
8
,
field_default
(
17
)
),
(
field_name_pad
(
"ip_header_checksum"
),
" "
,
16
,
field_default
(
0
)
),
(
field_name_pad
(
"ip_src_addr"
),
" "
,
32
,
field_default
(
0
)
),
(
field_name_pad
(
"ip_dst_addr"
),
" "
,
32
,
field_default
(
0
)
),
(
field_name_pad
(
"udp_src_port"
),
" "
,
16
,
field_default
(
0
)
),
(
field_name_pad
(
"udp_dst_port"
),
" "
,
16
,
field_default
(
0
)
),
(
field_name_pad
(
"udp_total_length"
),
" "
,
16
,
field_default
(
0
)
),
(
field_name_pad
(
"udp_checksum"
),
" "
,
16
,
field_default
(
0
)
),
(
field_name_pad
(
"usr_sync"
),
" "
,
1
,
field_default
(
1
)
),
(
field_name_pad
(
"usr_bsn"
),
" "
,
60
,
field_default
(
0
)
),
(
field_name_pad
(
"usr_hdr_field_0"
),
" "
,
7
,
field_default
(
0
)
),
(
field_name_pad
(
"usr_hdr_field_1"
),
" "
,
9
,
field_default
(
0
)
),
(
field_name_pad
(
"usr_hdr_field_2"
),
" "
,
10
,
field_default
(
0
)
),
(
field_name_pad
(
"usr_hdr_field_3"
),
" "
,
33
,
field_default
(
0
)
),
(
field_name_pad
(
"usr_hdr_field_4"
),
" "
,
5
,
field_default
(
0
)
),
(
field_name_pad
(
"usr_hdr_field_5"
),
" "
,
8
,
field_default
(
0
)
),
(
field_name_pad
(
"usr_hdr_field_6"
),
" "
,
27
,
field_default
(
0
)
),
(
field_name_pad
(
"usr_hdr_word_align"
),
" "
,
16
,
field_default
(
0
)
)
);
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
CONSTANT
c_dp_clk_period
:
TIME
:
=
5
ns
;
CONSTANT
c_nof_streams
:
POSITIVE
:
=
1
;
CONSTANT
hdr_fields_rst
:
t_slv_1024_arr
(
c_nof_streams
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
(
OTHERS
=>
'0'
));
SIGNAL
dp_rst
:
STD_LOGIC
;
SIGNAL
dp_clk
:
STD_LOGIC
:
=
'0'
;
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
SIGNAL
toggle
:
BOOLEAN
:
=
FALSE
;
SIGNAL
counter
:
NATURAL
:
=
0
;
SIGNAL
in_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
snk_in_arr
:
t_dp_sosi_arr
(
c_nof_streams
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
c_dp_sosi_rst
);
SIGNAL
snk_out_arr
:
t_dp_siso_arr
(
c_nof_streams
-1
DOWNTO
0
);
SIGNAL
src_in_arr
:
t_dp_siso_arr
(
c_nof_streams
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
c_dp_siso_rdy
);
SIGNAL
src_out_arr
:
t_dp_sosi_arr
(
c_nof_streams
-1
DOWNTO
0
);
SIGNAL
hdr_fields_in_arr
:
t_slv_1024_arr
(
c_nof_streams
-1
DOWNTO
0
);
SIGNAL
hdr_fields_out_arr
:
t_slv_1024_arr
(
c_nof_streams
-1
DOWNTO
0
);
SIGNAL
hdr_fields_wrong_arr
:
t_slv_1024_arr
(
c_nof_streams
-1
DOWNTO
0
);
BEGIN
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
dp_clk
<=
NOT
dp_clk
OR
tb_end
AFTER
c_dp_clk_period
/
2
;
dp_rst
<=
'1'
,
'0'
AFTER
c_dp_clk_period
*
5
;
gen_hdr_in
:
FOR
i
IN
0
TO
c_nof_streams
-1
GENERATE
hdr_fields_in_arr
(
i
)(
field_hi
(
c_hdr_field_arr
,
"eth_dst_mac"
)
DOWNTO
field_lo
(
c_hdr_field_arr
,
"eth_dst_mac"
))
<=
c_correct_mac
;
hdr_fields_in_arr
(
i
)(
field_hi
(
c_hdr_field_arr
,
"ip_dst_addr"
)
DOWNTO
field_lo
(
c_hdr_field_arr
,
"ip_dst_addr"
))
<=
c_correct_ip
;
hdr_fields_in_arr
(
i
)(
field_hi
(
c_hdr_field_arr
,
"udp_dst_port"
)
DOWNTO
field_lo
(
c_hdr_field_arr
,
"udp_dst_port"
))
<=
TO_UVEC
(
c_correct_port
,
16
);
hdr_fields_in_arr
(
i
)(
field_hi
(
c_hdr_field_arr
,
"ip_total_length"
)
DOWNTO
field_lo
(
c_hdr_field_arr
,
"ip_total_length"
))
<=
TO_UVEC
(
c_correct_length
,
16
);
END
GENERATE
;
gen_hdr_wrong
:
FOR
i
IN
0
TO
c_nof_streams
-1
GENERATE
hdr_fields_wrong_arr
(
i
)(
field_hi
(
c_hdr_field_arr
,
"eth_dst_mac"
)
DOWNTO
field_lo
(
c_hdr_field_arr
,
"eth_dst_mac"
))
<=
c_wrong_mac
;
hdr_fields_wrong_arr
(
i
)(
field_hi
(
c_hdr_field_arr
,
"ip_dst_addr"
)
DOWNTO
field_lo
(
c_hdr_field_arr
,
"ip_dst_addr"
))
<=
c_wrong_ip
;
hdr_fields_wrong_arr
(
i
)(
field_hi
(
c_hdr_field_arr
,
"udp_dst_port"
)
DOWNTO
field_lo
(
c_hdr_field_arr
,
"udp_dst_port"
))
<=
TO_UVEC
(
c_wrong_port
,
16
);
hdr_fields_wrong_arr
(
i
)(
field_hi
(
c_hdr_field_arr
,
"ip_total_length"
)
DOWNTO
field_lo
(
c_hdr_field_arr
,
"ip_total_length"
))
<=
TO_UVEC
(
c_wrong_length
,
16
);
END
GENERATE
;
p_stimuli
:
PROCESS
BEGIN
proc_common_wait_some_cycles
(
dp_clk
,
10
);
-- Generate a datastream.
WHILE
tb_end
=
'0'
LOOP
in_sosi
.
valid
<=
'1'
;
in_sosi
.
sop
<=
'1'
;
proc_common_wait_some_cycles
(
dp_clk
,
1
);
in_sosi
.
sop
<=
'0'
;
proc_common_wait_some_cycles
(
dp_clk
,
63
);
in_sosi
.
eop
<=
'1'
;
proc_common_wait_some_cycles
(
dp_clk
,
1
);
in_sosi
.
eop
<=
'0'
;
in_sosi
.
valid
<=
'0'
;
proc_common_wait_some_cycles
(
dp_clk
,
1
);
END
LOOP
;
END
PROCESS
;
gen_connect
:
FOR
I
IN
0
TO
c_nof_streams
-1
GENERATE
snk_in_arr
(
I
)
<=
in_sosi
;
END
GENERATE
;
p_special_stimuli
:
PROCESS
(
in_sosi
.
sop
)
BEGIN
IF
in_sosi
.
sop
=
'1'
THEN
counter
<=
counter
+
1
;
IF
toggle
THEN
hdr_fields_out_arr
<=
hdr_fields_in_arr
;
ELSE
hdr_fields_out_arr
<=
hdr_fields_wrong_arr
;
END
IF
;
toggle
<=
NOT
toggle
;
ELSE
hdr_fields_out_arr
<=
hdr_fields_rst
;
END
IF
;
IF
c_nof_packets
+
1
<=
counter
THEN
tb_end
<=
'1'
;
END
IF
;
END
PROCESS
;
dut
:
ENTITY
work
.
dp_offload_rx_filter
GENERIC
MAP
(
g_nof_streams
=>
c_nof_streams
,
--: POSITIVE;
g_data_w
=>
c_data_w
,
--: NATURAL;
g_hdr_field_arr
=>
c_hdr_field_arr
,
--: t_common_field_arr;
g_eth_dst_mac_ena
=>
TRUE
,
--: BOOLEAN;
g_ip_dst_addr_ena
=>
TRUE
,
--: BOOLEAN;
g_ip_total_length_ena
=>
TRUE
,
--: BOOLEAN;
g_udp_dst_port_ena
=>
TRUE
--: BOOLEAN
)
PORT
MAP
(
dp_rst
=>
dp_rst
,
dp_clk
=>
dp_clk
,
snk_in_arr
=>
snk_in_arr
,
snk_out_arr
=>
snk_out_arr
,
src_out_arr
=>
src_out_arr
,
src_in_arr
=>
src_in_arr
,
hdr_fields_out_arr
=>
hdr_fields_out_arr
,
hdr_fields_in_arr
=>
hdr_fields_in_arr
);
END
tb
;
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