Initial commit

libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+
+ENTITY dp_offload_rx_filter IS
+  GENERIC (   
+  	g_bypass							: BOOLEAN  := FALSE;
+    g_nof_streams         : POSITIVE := 1;
+    g_data_w              : NATURAL; 
+    g_hdr_field_arr       : t_common_field_arr;
+    g_eth_dst_mac_ena     : BOOLEAN;
+    g_ip_dst_addr_ena     : BOOLEAN;
+    g_ip_total_length_ena : BOOLEAN;
+    g_udp_dst_port_ena    : BOOLEAN     
+  ); 
+  PORT (
+    
+    dp_rst            : IN  STD_LOGIC;
+    dp_clk            : IN  STD_LOGIC; 
+                                              
+    snk_in_arr        : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); 
+    snk_out_arr       : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+                      
+    src_out_arr       : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); 
+    src_in_arr        : IN  t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+    
+    hdr_fields_out_arr: IN t_slv_1024_arr(g_nof_streams-1 DOWNTO 0);
+    hdr_fields_in_arr : IN t_slv_1024_arr(g_nof_streams-1 DOWNTO 0)
+  );
+END dp_offload_rx_filter;
+
+
+ARCHITECTURE str OF dp_offload_rx_filter  IS 
+                                         
+  CONSTANT c_header_w : NATURAL := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"));
+  CONSTANT c_nof_words: NATURAL := c_header_w/g_data_w;
+  
+  CONSTANT c_head : NATURAL := 1;
+  CONSTANT c_tail : NATURAL := 0;
+  
+  SUBTYPE eth_dst_mac_range     IS NATURAL RANGE field_hi(g_hdr_field_arr, "eth_dst_mac"    ) DOWNTO field_lo(g_hdr_field_arr, "eth_dst_mac");
+  SUBTYPE ip_total_length_range IS NATURAL RANGE field_hi(g_hdr_field_arr, "ip_total_length") DOWNTO field_lo(g_hdr_field_arr, "ip_total_length");    
+  SUBTYPE ip_dst_addr_range     IS NATURAL RANGE field_hi(g_hdr_field_arr, "ip_dst_addr"    ) DOWNTO field_lo(g_hdr_field_arr, "ip_dst_addr");
+  SUBTYPE udp_dst_port_range    IS NATURAL RANGE field_hi(g_hdr_field_arr, "udp_dst_port"   ) DOWNTO field_lo(g_hdr_field_arr, "udp_dst_port");
+  
+  TYPE reg_type IS RECORD
+    valid       : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+    src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+  END RECORD;
+
+  SIGNAL r, rin : reg_type;
+  
+BEGIN
+  
+  snk_out_arr <= src_in_arr;
+  
+  gen_bypass : IF g_bypass=TRUE GENERATE
+    src_out_arr <= snk_in_arr;
+  END GENERATE; 
+  
+  no_bypass : IF g_bypass=FALSE GENERATE
+    p_comb : PROCESS(hdr_fields_out_arr, snk_in_arr, r, dp_rst)
+      VARIABLE v : reg_type;
+    BEGIN   
+      v := r; 
+          
+      v.src_out_arr := snk_in_arr; 
+      check : FOR i in 0 TO g_nof_streams-1 LOOP
+        IF snk_in_arr(i).sop = '1' THEN   
+          v.valid(i) := '1';
+          
+          IF g_eth_dst_mac_ena     = TRUE AND NOT(hdr_fields_out_arr(i)(eth_dst_mac_range)     = hdr_fields_in_arr(i)(eth_dst_mac_range)     ) THEN
+            v.valid(i) := '0';
+          END IF;
+          
+          IF g_ip_total_length_ena = TRUE AND NOT(hdr_fields_out_arr(i)(ip_total_length_range) = hdr_fields_in_arr(i)(ip_total_length_range) ) THEN
+            v.valid(i) := '0';
+          END IF;            
+                             
+          IF g_ip_dst_addr_ena     = TRUE AND NOT(hdr_fields_out_arr(i)(ip_dst_addr_range)     = hdr_fields_in_arr(i)(ip_dst_addr_range)     ) THEN
+            v.valid(i) := '0';   
+          END IF;
+           
+          IF g_udp_dst_port_ena    = TRUE AND NOT(hdr_fields_out_arr(i)(udp_dst_port_range)    = hdr_fields_in_arr(i)(udp_dst_port_range)    ) THEN
+            v.valid(i) := '0';   
+          END IF;      
+         
+        END IF; 
+      END LOOP check;        
+    
+      IF(dp_rst = '1') THEN 
+        v.src_out_arr := (OTHERS => c_dp_sosi_rst);
+        v.valid       := (OTHERS => '0');
+      END IF;
+      
+      rin <= v;
+      
+    END PROCESS;
+    
+    
+    PROCESS(r)
+    BEGIN 
+      src_out_arr   <= r.src_out_arr;
+      set_val : FOR i in 0 TO g_nof_streams-1 LOOP  
+        src_out_arr(i).valid <= r.valid(i) AND r.src_out_arr(i).valid; 
+        src_out_arr(i).sop   <= r.valid(i) AND r.src_out_arr(i).sop;
+        src_out_arr(i).eop   <= r.valid(i) AND r.src_out_arr(i).eop;
+      END LOOP set_val;
+    END PROCESS; 
+    
+    p_regs : PROCESS(dp_clk)
+    BEGIN 
+      IF RISING_EDGE(dp_clk) THEN 
+        r <= rin; 
+      END IF; 
+    END PROCESS;
+  END GENERATE;        
+END str;