From 5fed528c0a9a11bcfcce231ea1cb061d035da41a Mon Sep 17 00:00:00 2001 From: David Brouwer <dbrouwer@astron.nl> Date: Wed, 8 Nov 2023 12:01:00 +0100 Subject: [PATCH] =?UTF-8?q?Based=20on=20ip=5Farria10=5Fe2sg/ram/ip=5Farria?= =?UTF-8?q?10=5Fe2sg=5Fcrw=5Fcrw.vhd.=20Updated=20information=20header.=20?= =?UTF-8?q?Changed=20the=20technology=5Fname=20from=20ip=5Farria10=5Fe2sg?= =?UTF-8?q?=20to=20ip=5Fagi027=5Fxxxx=20and=20crw=5Fcrw=20to=20rw=5Frw.=20?= =?UTF-8?q?And=20copied=20in=20the=20component=20declaration=20from=20gene?= =?UTF-8?q?rated/ram=5F2port=5F2040/sim/ip=5Fagi027=5Fxxxx=5Fram=5Frw=5Frw?= =?UTF-8?q?=5Fram=5F2port=5F2040=5Fuxwhvmq.vhd=20and=20compared=20it=20als?= =?UTF-8?q?o=20to=20ip=5Farria10=5Fe2sg=5Fcrw=5Fcrw=5Fram=5F2port=5F2000?= =?UTF-8?q?=5Fzxnv4ey.=20Checked=20the=20differences=20between=20this=20un?= =?UTF-8?q?derlying=20files.=20The=20extra=20generics=20are=20added=20and?= =?UTF-8?q?=20commented=20out.=20The=20generics=20that=20are=20different?= =?UTF-8?q?=20address=5Freg=5Fb,=20indata=5Freg=5Fb=20and=20outdata=5Freg?= =?UTF-8?q?=5Fb=20are=20changed=20from=20=E2=80=9CCLOCK1=E2=80=9D=20to=20?= =?UTF-8?q?=E2=80=9CCLOCK0=E2=80=9D.=20Generic=20read=5Fng=5Fwrite=5Fmode?= =?UTF-8?q?=5Fmixed=5Fports=20=3D>=20"OLD=5FDATA"=20despite=20the=20genera?= =?UTF-8?q?ted=20HDL=20file=20has=20default=20value=20"DONT=5FCARE".=20Cha?= =?UTF-8?q?nged=20the=20ports=20to=20one=20clock.=20Removed=20the=20consta?= =?UTF-8?q?nt=20c=5Foutdata=5Freg=5Fb=20and=20change=20constant=20c=5Foutd?= =?UTF-8?q?ata=5Freg=5Fa=20to=20c=5Foutdata=5Freg.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../ram/ip_agi027_xxxx_ram_rw_rw.vhd | 193 ++++++++++++++++++ 1 file changed, 193 insertions(+) create mode 100644 libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd new file mode 100644 index 0000000000..b66a6c4c31 --- /dev/null +++ b/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd @@ -0,0 +1,193 @@ +-- ----------------------------------------------------------------------------- +-- +-- Copyright 2023 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +-- ----------------------------------------------------------------------------- +-- +-- Author: D.F. Brouwer +-- Purpose: +-- RadioHDL wrapper / Instantiate RAM IP with generics +-- Description: +-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_rw_rw_ram_2port_2040_uxwhvmq.vhd + +library ieee, technology_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use technology_lib.technology_pkg.all; + +library altera_lnsim; +use altera_lnsim.altera_lnsim_components.all; + +entity ip_agi027_xxxx_ram_rw_rw is + generic ( + g_inferred : boolean := false; + g_adr_w : natural := 5; + g_dat_w : natural := 8; + g_nof_words : natural := 2**5; + g_rd_latency : natural := 1; -- choose 1 or 2 + g_init_file : string := "UNUSED" + ); + port ( + address_a : in std_logic_vector(g_adr_w - 1 downto 0); + address_b : in std_logic_vector(g_adr_w - 1 downto 0); + clk : in std_logic := '1'; + data_a : in std_logic_vector(g_dat_w - 1 downto 0); + data_b : in std_logic_vector(g_dat_w - 1 downto 0); + wren_a : in std_logic := '0'; + wren_b : in std_logic := '0'; + q_a : out std_logic_vector(g_dat_w - 1 downto 0); + q_b : out std_logic_vector(g_dat_w - 1 downto 0) + ); +end ip_agi027_xxxx_ram_rw_rw; + +architecture SYN of ip_agi027_xxxx_ram_rw_rw is + constant c_outdata_reg : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0"); + + component altera_syncram + generic ( + address_reg_b : string; + clock_enable_input_a : string; + clock_enable_input_b : string; + clock_enable_output_a : string; + clock_enable_output_b : string; + indata_reg_b : string; + init_file : string; + -- enable_force_to_zero : string; + intended_device_family : string; + lpm_type : string; + numwords_a : integer; + numwords_b : integer; + operation_mode : string; + outdata_aclr_a : string; + -- outdata_sclr_a : string; + outdata_aclr_b : string; + -- outdata_sclr_b : string; + outdata_reg_a : string; + outdata_reg_b : string; + power_up_uninitialized : string; + read_during_write_mode_port_a : string; + read_during_write_mode_port_b : string; + read_during_write_mode_mixed_ports : string; + widthad_a : integer; + widthad_b : integer; + width_a : integer; + width_b : integer; + width_byteena_a : integer; + width_byteena_b : integer + ); + port ( + address_a : in std_logic_vector(g_adr_w - 1 downto 0); + address_b : in std_logic_vector(g_adr_w - 1 downto 0); + clock0 : in std_logic; + data_a : in std_logic_vector(g_dat_w - 1 downto 0); + data_b : in std_logic_vector(g_dat_w - 1 downto 0); + wren_a : in std_logic; + wren_b : in std_logic; + q_a : out std_logic_vector(g_dat_w - 1 downto 0); + q_b : out std_logic_vector(g_dat_w - 1 downto 0) + ); + end component; + + -- Is used for gen_inferred: + signal addr_a : natural range 0 to g_nof_words - 1; + signal addr_b : natural range 0 to g_nof_words - 1; + + signal out_a : std_logic_vector(g_dat_w - 1 downto 0); + signal out_b : std_logic_vector(g_dat_w - 1 downto 0); + + signal reg_a : std_logic_vector(g_dat_w - 1 downto 0); + signal reg_b : std_logic_vector(g_dat_w - 1 downto 0); +begin + assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_rw_rw : read latency must be 1 (default) or 2" severity FAILURE; + + gen_ip : if g_inferred = false generate + u_altera_syncram : altera_syncram + generic map ( + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK0", + init_file => g_init_file, + --enable_force_to_zero => "FALSE", + intended_device_family => "Agilex 7", + lpm_type => "altera_syncram", + numwords_a => g_nof_words, + numwords_b => g_nof_words, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + --outdata_sclr_a => "NONE", + outdata_aclr_b => "NONE", + --outdata_sclr_b => "NONE", + outdata_reg_a => c_outdata_reg, + outdata_reg_b => c_outdata_reg, + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_mixed_ports => "OLD_DATA", + --read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => g_adr_w, + widthad_b => g_adr_w, + width_a => g_dat_w, + width_b => g_dat_w, + width_byteena_a => 1, + width_byteena_b => 1 + ) + port map ( + address_a => address_a, + address_b => address_b, + clock0 => clk, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + + end generate; + + gen_inferred : if g_inferred = true generate + addr_a <= to_integer(unsigned(address_a)); + addr_b <= to_integer(unsigned(address_b)); + + u_mem : entity work.ip_agi027_xxxx_true_dual_port_ram_single_clock + generic map ( + DATA_WIDTH => g_dat_w, + ADDR_WIDTH => g_adr_w + ) + port map ( + clk => clk, + addr_a => addr_a, + addr_b => addr_b, + data_a => data_a, + data_b => data_b, + we_a => wren_a, + we_b => wren_b, + q_a => out_a, + q_b => out_b + ); + + reg_a <= out_a when rising_edge(clk); + reg_b <= out_b when rising_edge(clk); + + q_a <= out_a when g_rd_latency = 1 else reg_a; + q_b <= out_b when g_rd_latency = 1 else reg_b; + end generate; + +end SYN; -- GitLab