Improve input register stage, to avoid direct use of ref_sync for cnt_en..

libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd

@@ -114,7 +114,9 @@ ARCHITECTURE rtl OF dp_strobe_total_count IS
 
   -- Registers in dp_clk domain
   SIGNAL ref_sync_reg       : STD_LOGIC := '0';
+  SIGNAL ref_sync_reg2      : STD_LOGIC := '0';
   SIGNAL in_strobe_reg_arr  : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL in_strobe_reg2_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0) := (OTHERS=>'0');
   SIGNAL rd_reg             : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
   SIGNAL mm_cnt_clr         : STD_LOGIC;
   SIGNAL cnt_clr            : STD_LOGIC;
@@ -140,15 +142,21 @@ BEGIN
       out_pulse => cnt_clr
     );
 
+  -- Register inputs to ease timing closure
   -- . register ref_sync to ease timing closure for ref_sync fanout
-  ref_sync_reg <= ref_sync WHEN rising_edge(dp_clk);
-
   -- . register in_strobe_arr to preserve alignment with ref_sync
+  ref_sync_reg <= ref_sync WHEN rising_edge(dp_clk);
   in_strobe_reg_arr <= in_strobe_arr WHEN rising_edge(dp_clk);
 
+  -- Register inputs again to be able to align registered cnt_en and
+  -- pipelined ref_sync pulse
+  ref_sync_reg2 <= ref_sync_reg WHEN rising_edge(dp_clk);
+  in_strobe_reg2_arr <= in_strobe_reg_arr WHEN rising_edge(dp_clk);
+
   -- . clear strobe counters immediately at cnt_clr
-  -- . start strobe counters after ref_sync, e.g. to align strobe counters in different nodes in
-  --   case the input was (already) active during the cnt_clr
+  -- . start strobe counters after ref_sync, e.g. to align strobe counters
+  --   in different nodes in case the input was (already) active during
+  --   the cnt_clr
   p_cnt_en : PROCESS(dp_rst, dp_clk)
   BEGIN
     IF dp_rst = '1' THEN
@@ -156,7 +164,8 @@ BEGIN
     ELSIF rising_edge(dp_clk) THEN
       IF cnt_clr = '1' THEN
         cnt_en <= '0';
-      ELSIF ref_sync = '1' THEN  -- use ref_sync have cnt_en aligned with ref_sync_reg
+      ELSIF ref_sync_reg = '1' THEN
+        -- use ref_sync_reg have cnt_en high aligned with ref_sync_reg2
         cnt_en <= '1';
       END IF;
     END IF;
@@ -181,13 +190,14 @@ BEGIN
     );
   END GENERATE;
 
-  -- Hold counter values at ref_sync_reg to have stable values for MM read for comparision between nodes
+  -- Hold counter values at ref_sync_reg2 to have stable values for MM read
+  -- for comparision between nodes
   p_hold_counters : PROCESS(dp_clk)
   BEGIN
     IF rising_edge(dp_clk) THEN
       IF cnt_clr = '1' THEN
         hold_cnt_arr <= (OTHERS=>(OTHERS=>'0'));
-      ELSIF ref_sync_reg = '1' THEN
+      ELSIF ref_sync_reg2 = '1' THEN
         hold_cnt_arr <= cnt_arr;
       END IF;
     END IF;