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Commit 5e18ba1b authored by Eric Kooistra's avatar Eric Kooistra
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Fit too long lines within 120 char.

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libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
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− 61
View file @ 5e18ba1b
...@@ -46,9 +46,12 @@ entity ip_arria10_e1sg_jesd204b is ...@@ -46,9 +46,12 @@ entity ip_arria10_e1sg_jesd204b is
); );
port ( port (
-- JESD204B external signals -- JESD204B external signals
jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock
jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk -- reference pin
jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization/syncronization phase jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase with
-- respect to jesd204b_device_clk
jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization /
-- syncronization phase
-- Data to fabric -- Data to fabric
rx_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data out to fabric rx_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data out to fabric
...@@ -76,10 +79,11 @@ architecture str of ip_arria10_e1sg_jesd204b is ...@@ -76,10 +79,11 @@ architecture str of ip_arria10_e1sg_jesd204b is
-- but using mm_addr_w = 8 and span = 256 words is fine too. -- but using mm_addr_w = 8 and span = 256 words is fine too.
constant c_jesd204b_mm_addr_w : natural := 8; constant c_jesd204b_mm_addr_w : natural := 8;
constant c_jesd204b_rx_data_w : natural := 32; constant c_jesd204b_rx_data_w : natural := 32;
constant c_jesd204b_rx_framer_data_w : natural := c_jesd204b_rx_data_w / 2; -- IP outputs two samples in parallel constant c_jesd204b_rx_framer_data_w : natural := c_jesd204b_rx_data_w / 2; -- = 16, two samples in parallel
constant c_jesd204b_rx_somf_w : natural := c_jesd204b_rx_data_w / 8; -- One somf bit per octet constant c_jesd204b_rx_somf_w : natural := c_jesd204b_rx_data_w / 8; -- = 4, one somf bit per octet
constant c_jesd204b_rx_framer_somf_w : natural := c_jesd204b_rx_somf_w / 2; -- IP outputs two samples in parallel constant c_jesd204b_rx_framer_somf_w : natural := c_jesd204b_rx_somf_w / 2; -- = 2, two samples in parallel
constant c_nof_sync_n_per_group : natural := sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n); constant c_nof_sync_n_per_group : natural := sel_a_b(g_nof_streams / g_nof_sync_n = 0,
1, g_nof_streams / g_nof_sync_n);
-- JESD204 control status registers -- JESD204 control status registers
signal jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0); signal jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
...@@ -92,8 +96,8 @@ architecture str of ip_arria10_e1sg_jesd204b is ...@@ -92,8 +96,8 @@ architecture str of ip_arria10_e1sg_jesd204b is
signal rxlink_clk : std_logic; signal rxlink_clk : std_logic;
signal jesd204b_avs_clk : std_logic; signal jesd204b_avs_clk : std_logic;
-- Reset and control signals -- Reset and control signals, 1 bit per lane
signal dev_lane_aligned : std_logic_vector(g_nof_streams - 1 downto 0); -- 1 bit, each interface channel has 1 lane signal dev_lane_aligned : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_analogreset_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rx_analogreset_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_cal_busy_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rx_cal_busy_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_digitalreset_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rx_digitalreset_arr : std_logic_vector(g_nof_streams - 1 downto 0);
...@@ -127,9 +131,10 @@ architecture str of ip_arria10_e1sg_jesd204b is ...@@ -127,9 +131,10 @@ architecture str of ip_arria10_e1sg_jesd204b is
signal jesd204b_rx_link_valid_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal jesd204b_rx_link_valid_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal jesd204b_rx_somf_arr : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0); signal jesd204b_rx_somf_arr : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0);
signal jesd204b_sync_n_internal_arr : std_logic_vector(g_nof_streams - 1 downto 0); -- output to control ADC initialization/syncronization phase -- output to control ADC initialization / syncronization phase
signal jesd204b_sync_n_enabled_arr : std_logic_vector(g_nof_streams - 1 downto 0); -- output to control ADC initialization/syncronization phase signal jesd204b_sync_n_internal_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal jesd204b_sync_n_combined_arr : std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization/syncronization phase signal jesd204b_sync_n_enabled_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal jesd204b_sync_n_combined_arr : std_logic_vector(g_nof_sync_n - 1 downto 0);
-- Component declarations for the IP blocks -- Component declarations for the IP blocks
...@@ -150,15 +155,15 @@ architecture str of ip_arria10_e1sg_jesd204b is ...@@ -150,15 +155,15 @@ architecture str of ip_arria10_e1sg_jesd204b is
csr_s : out std_logic_vector(4 downto 0); -- export csr_s : out std_logic_vector(4 downto 0); -- export
dev_lane_aligned : out std_logic; -- export dev_lane_aligned : out std_logic; -- export
dev_sync_n : out std_logic; -- export dev_sync_n : out std_logic; -- export
jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect jesd204_rx_avs_chipselect : in std_logic := 'X';
jesd204_rx_avs_address : in std_logic_vector(c_jesd204b_mm_addr_w - 1 downto 0) := (others => 'X'); -- address jesd204_rx_avs_address : in std_logic_vector(c_jesd204b_mm_addr_w - 1 downto 0) := (others => 'X');
jesd204_rx_avs_read : in std_logic := 'X'; -- read jesd204_rx_avs_read : in std_logic := 'X';
jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0);
jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest jesd204_rx_avs_waitrequest : out std_logic;
jesd204_rx_avs_write : in std_logic := 'X'; -- write jesd204_rx_avs_write : in std_logic := 'X';
jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
jesd204_rx_avs_clk : in std_logic := 'X'; -- clk jesd204_rx_avs_clk : in std_logic := 'X';
jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n jesd204_rx_avs_rst_n : in std_logic := 'X';
jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
...@@ -232,7 +237,8 @@ architecture str of ip_arria10_e1sg_jesd204b is ...@@ -232,7 +237,8 @@ architecture str of ip_arria10_e1sg_jesd204b is
end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12; end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
begin begin
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer. -- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e1sg_jesd204b and causes a reset on the rx_rst output. -- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e1sg_jesd204b and
-- causes a reset on the rx_rst output.
rx_clk <= rxframe_clk; rx_clk <= rxframe_clk;
rx_rst <= not core_pll_locked; rx_rst <= not core_pll_locked;
...@@ -252,7 +258,6 @@ begin ...@@ -252,7 +258,6 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- The JESD204 IP (rx only) -- The JESD204 IP (rx only)
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
gen_jesd204b_rx_freqsel : if g_jesd_freq = "200MHz" generate gen_jesd204b_rx_freqsel : if g_jesd_freq = "200MHz" generate
u_ip_arria10_e1sg_jesd204b_rx_200MHz : ip_arria10_e1sg_jesd204b_rx_200MHz u_ip_arria10_e1sg_jesd204b_rx_200MHz : ip_arria10_e1sg_jesd204b_rx_200MHz
port map ( port map (
...@@ -287,10 +292,12 @@ begin ...@@ -287,10 +292,12 @@ begin
jesd204_rx_dlb_kchar_data => (others => '0'), -- debug/loopback testing jesd204_rx_dlb_kchar_data => (others => '0'), -- debug/loopback testing
jesd204_rx_frame_error => '0', -- jesd204_rx_frame_error.export jesd204_rx_frame_error => '0', -- jesd204_rx_frame_error.export
jesd204_rx_int => OPEN, -- Connected to status IO in example design jesd204_rx_int => OPEN, -- Connected to status IO in example design
jesd204_rx_link_data => jesd204b_rx_link_data_arr(i * c_jesd204b_rx_data_w + c_jesd204b_rx_data_w - 1 downto i * c_jesd204b_rx_data_w), jesd204_rx_link_data => jesd204b_rx_link_data_arr(i * c_jesd204b_rx_data_w + c_jesd204b_rx_data_w - 1
downto i * c_jesd204b_rx_data_w),
jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i), jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i),
jesd204_rx_link_ready => '1', jesd204_rx_link_ready => '1',
pll_ref_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63) pll_ref_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame
-- clock IOPLL (Intel JESD204B-UG p63)
rx_analogreset => rx_analogreset_arr(I downto I), rx_analogreset => rx_analogreset_arr(I downto I),
rx_cal_busy => rx_cal_busy_arr(I downto I), rx_cal_busy => rx_cal_busy_arr(I downto I),
rx_digitalreset => rx_digitalreset_arr(I downto I), rx_digitalreset => rx_digitalreset_arr(I downto I),
...@@ -300,7 +307,8 @@ begin ...@@ -300,7 +307,8 @@ begin
rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69) rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63) rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
sof => OPEN, sof => OPEN,
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto c_jesd204b_rx_somf_w * i), somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1
downto c_jesd204b_rx_somf_w * i),
sysref => jesd204b_sysref_2 sysref => jesd204b_sysref_2
); );
...@@ -360,7 +368,9 @@ begin ...@@ -360,7 +368,9 @@ begin
out_rst => rxframe_rst_arr(i) out_rst => rxframe_rst_arr(i)
); );
rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i) = '1' or xcvr_rst_ctrl_rx_ready_arr(i) = '1' else '0'; rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i) = '1' or
xcvr_rst_ctrl_rx_ready_arr(i) = '1' else '0';
-- synchronize rx_xcvr_ready_in_arr to mm_clk -- synchronize rx_xcvr_ready_in_arr to mm_clk
u_common_async_rx_xcvr_ready : entity common_lib.common_async u_common_async_rx_xcvr_ready : entity common_lib.common_async
generic map ( generic map (
...@@ -396,11 +406,19 @@ begin ...@@ -396,11 +406,19 @@ begin
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= (others => '0'); rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= (others => '0');
else else
if f2_div1_cnt_arr(i) = '1' then if f2_div1_cnt_arr(i) = '1' then
rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto c_jesd204b_rx_data_w * i); rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <=
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto c_jesd204b_rx_somf_w * i); jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
c_jesd204b_rx_data_w * i);
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <=
jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto
c_jesd204b_rx_somf_w * i);
else else
rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w); rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <=
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w); jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w);
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <=
jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto
c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w);
end if; end if;
f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i); f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i);
end if; end if;
...@@ -420,13 +438,11 @@ begin ...@@ -420,13 +438,11 @@ begin
jesd204b_sysref_1 <= '0'; jesd204b_sysref_1 <= '0';
jesd204b_sysref_2 <= '0'; jesd204b_sysref_2 <= '0';
jesd204b_sync_n_arr <= (others => '0'); jesd204b_sync_n_arr <= (others => '0');
else elsif rising_edge(rxlink_clk) then
if rising_edge(rxlink_clk) then
jesd204b_sysref_1 <= jesd204b_sysref; jesd204b_sysref_1 <= jesd204b_sysref;
jesd204b_sysref_2 <= jesd204b_sysref_1; jesd204b_sysref_2 <= jesd204b_sysref_1;
jesd204b_sync_n_arr <= jesd204b_sync_n_combined_arr; jesd204b_sync_n_arr <= jesd204b_sync_n_combined_arr;
end if; end if;
end if;
end process; end process;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -480,20 +496,26 @@ begin ...@@ -480,20 +496,26 @@ begin
u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12 u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
port map ( port map (
clock => rxlink_clk, clock => rxlink_clk,
reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design, the reset input is synchronised internally. reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design, the
rx_analogreset => rx_analogreset_arr, -- output to reset RX PMA. Release before deasserting link and avs resets (Intel JESD204B-UG p70) -- reset input is synchronised internally.
rx_analogreset => rx_analogreset_arr, -- output to reset RX PMA. Release before deasserting
-- link and avs resets (Intel JESD204B-UG p70)
rx_cal_busy => rx_cal_busy_arr, -- input from PHY rx_cal_busy => rx_cal_busy_arr, -- input from PHY
rx_digitalreset => rx_digitalreset_arr, -- output to reset RX PCS. Release before deasserting link and avs resets (Intel JESD204B-UG p70) rx_digitalreset => rx_digitalreset_arr, -- output to reset RX PCS. Release before deasserting
-- link and avs resets (Intel JESD204B-UG p70)
rx_is_lockedtodata => rx_islockedtodata_arr, -- input from PHY rx_is_lockedtodata => rx_islockedtodata_arr, -- input from PHY
rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with
-- rx_csr_lane_powerdown to reset transceiver
); );
end generate; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE end generate; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_enable_sync_n : for i in 0 to g_nof_streams - 1 generate gen_enable_sync_n : for i in 0 to g_nof_streams - 1 generate
-- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used) -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output
-- is forced to '1', so that for the disabled (= inactive = not used)
-- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low. -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
-- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share -- The purpose of being able to disable inactive signal inputs is that this avoids that one
-- the sync_n_combined to become unavailable (see gen_group_sync_n). -- inactive signal input will cause all signal inputs in a group that share the sync_n_combined
-- to become unavailable (see gen_group_sync_n).
-- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) or jesd204b_disable_arr(i); jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) or jesd204b_disable_arr(i);
...@@ -503,7 +525,9 @@ begin ...@@ -503,7 +525,9 @@ begin
-- Group the SYNC_N outputs -- Group the SYNC_N outputs
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
gen_group_sync_n : for i in 0 to g_nof_sync_n - 1 generate gen_group_sync_n : for i in 0 to g_nof_sync_n - 1 generate
jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group * i + c_nof_sync_n_per_group - 1 downto c_nof_sync_n_per_group * i)); jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(
c_nof_sync_n_per_group * i + c_nof_sync_n_per_group - 1 downto
c_nof_sync_n_per_group * i));
end generate; end generate;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
......
libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+ 85
− 61
View file @ 5e18ba1b
...@@ -46,9 +46,12 @@ entity ip_arria10_e2sg_jesd204b is ...@@ -46,9 +46,12 @@ entity ip_arria10_e2sg_jesd204b is
); );
port ( port (
-- JESD204B external signals -- JESD204B external signals
jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock
jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk -- reference pin
jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization/syncronization phase jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase with
-- respect to jesd204b_device_clk
jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization /
-- syncronization phase
-- Data to fabric -- Data to fabric
rx_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data out to fabric rx_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data out to fabric
...@@ -76,10 +79,11 @@ architecture str of ip_arria10_e2sg_jesd204b is ...@@ -76,10 +79,11 @@ architecture str of ip_arria10_e2sg_jesd204b is
-- but using mm_addr_w = 8 and span = 256 words is fine too. -- but using mm_addr_w = 8 and span = 256 words is fine too.
constant c_jesd204b_mm_addr_w : natural := 8; constant c_jesd204b_mm_addr_w : natural := 8;
constant c_jesd204b_rx_data_w : natural := 32; constant c_jesd204b_rx_data_w : natural := 32;
constant c_jesd204b_rx_framer_data_w : natural := c_jesd204b_rx_data_w / 2; -- IP outputs two samples in parallel constant c_jesd204b_rx_framer_data_w : natural := c_jesd204b_rx_data_w / 2; -- = 16, two samples in parallel
constant c_jesd204b_rx_somf_w : natural := c_jesd204b_rx_data_w / 8; -- One somf bit per octet constant c_jesd204b_rx_somf_w : natural := c_jesd204b_rx_data_w / 8; -- = 4, one somf bit per octet
constant c_jesd204b_rx_framer_somf_w : natural := c_jesd204b_rx_somf_w / 2; -- IP outputs two samples in parallel constant c_jesd204b_rx_framer_somf_w : natural := c_jesd204b_rx_somf_w / 2; -- = 2, two samples in parallel
constant c_nof_sync_n_per_group : natural := sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n); constant c_nof_sync_n_per_group : natural := sel_a_b(g_nof_streams / g_nof_sync_n = 0,
1, g_nof_streams / g_nof_sync_n);
-- JESD204 control status registers -- JESD204 control status registers
signal jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0); signal jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
...@@ -92,8 +96,8 @@ architecture str of ip_arria10_e2sg_jesd204b is ...@@ -92,8 +96,8 @@ architecture str of ip_arria10_e2sg_jesd204b is
signal rxlink_clk : std_logic; signal rxlink_clk : std_logic;
signal jesd204b_avs_clk : std_logic; signal jesd204b_avs_clk : std_logic;
-- Reset and control signals -- Reset and control signals, 1 bit per lane
signal dev_lane_aligned : std_logic_vector(g_nof_streams - 1 downto 0); -- 1 bit, each interface channel has 1 lane signal dev_lane_aligned : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_analogreset_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rx_analogreset_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_cal_busy_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rx_cal_busy_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_digitalreset_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rx_digitalreset_arr : std_logic_vector(g_nof_streams - 1 downto 0);
...@@ -127,9 +131,10 @@ architecture str of ip_arria10_e2sg_jesd204b is ...@@ -127,9 +131,10 @@ architecture str of ip_arria10_e2sg_jesd204b is
signal jesd204b_rx_link_valid_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal jesd204b_rx_link_valid_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal jesd204b_rx_somf_arr : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0); signal jesd204b_rx_somf_arr : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0);
signal jesd204b_sync_n_internal_arr : std_logic_vector(g_nof_streams - 1 downto 0); -- output to control ADC initialization/syncronization phase -- output to control ADC initialization / syncronization phase
signal jesd204b_sync_n_enabled_arr : std_logic_vector(g_nof_streams - 1 downto 0); -- output to control ADC initialization/syncronization phase signal jesd204b_sync_n_internal_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal jesd204b_sync_n_combined_arr : std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization/syncronization phase signal jesd204b_sync_n_enabled_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal jesd204b_sync_n_combined_arr : std_logic_vector(g_nof_sync_n - 1 downto 0);
-- Component declarations for the IP blocks -- Component declarations for the IP blocks
...@@ -150,15 +155,15 @@ architecture str of ip_arria10_e2sg_jesd204b is ...@@ -150,15 +155,15 @@ architecture str of ip_arria10_e2sg_jesd204b is
csr_s : out std_logic_vector(4 downto 0); -- export csr_s : out std_logic_vector(4 downto 0); -- export
dev_lane_aligned : out std_logic; -- export dev_lane_aligned : out std_logic; -- export
dev_sync_n : out std_logic; -- export dev_sync_n : out std_logic; -- export
jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect jesd204_rx_avs_chipselect : in std_logic := 'X';
jesd204_rx_avs_address : in std_logic_vector(c_jesd204b_mm_addr_w - 1 downto 0) := (others => 'X'); -- address jesd204_rx_avs_address : in std_logic_vector(c_jesd204b_mm_addr_w - 1 downto 0) := (others => 'X');
jesd204_rx_avs_read : in std_logic := 'X'; -- read jesd204_rx_avs_read : in std_logic := 'X';
jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0);
jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest jesd204_rx_avs_waitrequest : out std_logic;
jesd204_rx_avs_write : in std_logic := 'X'; -- write jesd204_rx_avs_write : in std_logic := 'X';
jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
jesd204_rx_avs_clk : in std_logic := 'X'; -- clk jesd204_rx_avs_clk : in std_logic := 'X';
jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n jesd204_rx_avs_rst_n : in std_logic := 'X';
jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
...@@ -232,7 +237,8 @@ architecture str of ip_arria10_e2sg_jesd204b is ...@@ -232,7 +237,8 @@ architecture str of ip_arria10_e2sg_jesd204b is
end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12; end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
begin begin
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer. -- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e2sg_jesd204b and causes a reset on the rx_rst output. -- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e2sg_jesd204b and
-- causes a reset on the rx_rst output.
rx_clk <= rxframe_clk; rx_clk <= rxframe_clk;
rx_rst <= not core_pll_locked; rx_rst <= not core_pll_locked;
...@@ -252,7 +258,6 @@ begin ...@@ -252,7 +258,6 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- The JESD204 IP (rx only) -- The JESD204 IP (rx only)
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
gen_jesd204b_rx_freqsel : if g_jesd_freq = "200MHz" generate gen_jesd204b_rx_freqsel : if g_jesd_freq = "200MHz" generate
u_ip_arria10_e2sg_jesd204b_rx_200MHz : ip_arria10_e2sg_jesd204b_rx_200MHz u_ip_arria10_e2sg_jesd204b_rx_200MHz : ip_arria10_e2sg_jesd204b_rx_200MHz
port map ( port map (
...@@ -287,10 +292,12 @@ begin ...@@ -287,10 +292,12 @@ begin
jesd204_rx_dlb_kchar_data => (others => '0'), -- debug/loopback testing jesd204_rx_dlb_kchar_data => (others => '0'), -- debug/loopback testing
jesd204_rx_frame_error => '0', -- jesd204_rx_frame_error.export jesd204_rx_frame_error => '0', -- jesd204_rx_frame_error.export
jesd204_rx_int => OPEN, -- Connected to status IO in example design jesd204_rx_int => OPEN, -- Connected to status IO in example design
jesd204_rx_link_data => jesd204b_rx_link_data_arr(i * c_jesd204b_rx_data_w + c_jesd204b_rx_data_w - 1 downto i * c_jesd204b_rx_data_w), jesd204_rx_link_data => jesd204b_rx_link_data_arr(i * c_jesd204b_rx_data_w + c_jesd204b_rx_data_w - 1
downto i * c_jesd204b_rx_data_w),
jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i), jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i),
jesd204_rx_link_ready => '1', jesd204_rx_link_ready => '1',
pll_ref_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63) pll_ref_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame
-- clock IOPLL (Intel JESD204B-UG p63)
rx_analogreset => rx_analogreset_arr(I downto I), rx_analogreset => rx_analogreset_arr(I downto I),
rx_cal_busy => rx_cal_busy_arr(I downto I), rx_cal_busy => rx_cal_busy_arr(I downto I),
rx_digitalreset => rx_digitalreset_arr(I downto I), rx_digitalreset => rx_digitalreset_arr(I downto I),
...@@ -300,7 +307,8 @@ begin ...@@ -300,7 +307,8 @@ begin
rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69) rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63) rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
sof => OPEN, sof => OPEN,
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto c_jesd204b_rx_somf_w * i), somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1
downto c_jesd204b_rx_somf_w * i),
sysref => jesd204b_sysref_2 sysref => jesd204b_sysref_2
); );
...@@ -360,7 +368,9 @@ begin ...@@ -360,7 +368,9 @@ begin
out_rst => rxframe_rst_arr(i) out_rst => rxframe_rst_arr(i)
); );
rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i) = '1' or xcvr_rst_ctrl_rx_ready_arr(i) = '1' else '0'; rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i) = '1' or
xcvr_rst_ctrl_rx_ready_arr(i) = '1' else '0';
-- synchronize rx_xcvr_ready_in_arr to mm_clk -- synchronize rx_xcvr_ready_in_arr to mm_clk
u_common_async_rx_xcvr_ready : entity common_lib.common_async u_common_async_rx_xcvr_ready : entity common_lib.common_async
generic map ( generic map (
...@@ -396,11 +406,19 @@ begin ...@@ -396,11 +406,19 @@ begin
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= (others => '0'); rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= (others => '0');
else else
if f2_div1_cnt_arr(i) = '1' then if f2_div1_cnt_arr(i) = '1' then
rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto c_jesd204b_rx_data_w * i); rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <=
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto c_jesd204b_rx_somf_w * i); jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
c_jesd204b_rx_data_w * i);
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <=
jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto
c_jesd204b_rx_somf_w * i);
else else
rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w); rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <=
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w); jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w);
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <=
jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto
c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w);
end if; end if;
f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i); f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i);
end if; end if;
...@@ -420,13 +438,11 @@ begin ...@@ -420,13 +438,11 @@ begin
jesd204b_sysref_1 <= '0'; jesd204b_sysref_1 <= '0';
jesd204b_sysref_2 <= '0'; jesd204b_sysref_2 <= '0';
jesd204b_sync_n_arr <= (others => '0'); jesd204b_sync_n_arr <= (others => '0');
else elsif rising_edge(rxlink_clk) then
if rising_edge(rxlink_clk) then
jesd204b_sysref_1 <= jesd204b_sysref; jesd204b_sysref_1 <= jesd204b_sysref;
jesd204b_sysref_2 <= jesd204b_sysref_1; jesd204b_sysref_2 <= jesd204b_sysref_1;
jesd204b_sync_n_arr <= jesd204b_sync_n_combined_arr; jesd204b_sync_n_arr <= jesd204b_sync_n_combined_arr;
end if; end if;
end if;
end process; end process;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -480,20 +496,26 @@ begin ...@@ -480,20 +496,26 @@ begin
u_ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12 u_ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12
port map ( port map (
clock => rxlink_clk, clock => rxlink_clk,
reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design, the reset input is synchronised internally. reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design, the
rx_analogreset => rx_analogreset_arr, -- output to reset RX PMA. Release before deasserting link and avs resets (Intel JESD204B-UG p70) -- reset input is synchronised internally.
rx_analogreset => rx_analogreset_arr, -- output to reset RX PMA. Release before deasserting
-- link and avs resets (Intel JESD204B-UG p70)
rx_cal_busy => rx_cal_busy_arr, -- input from PHY rx_cal_busy => rx_cal_busy_arr, -- input from PHY
rx_digitalreset => rx_digitalreset_arr, -- output to reset RX PCS. Release before deasserting link and avs resets (Intel JESD204B-UG p70) rx_digitalreset => rx_digitalreset_arr, -- output to reset RX PCS. Release before deasserting
-- link and avs resets (Intel JESD204B-UG p70)
rx_is_lockedtodata => rx_islockedtodata_arr, -- input from PHY rx_is_lockedtodata => rx_islockedtodata_arr, -- input from PHY
rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with
-- rx_csr_lane_powerdown to reset transceiver
); );
end generate; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE end generate; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_enable_sync_n : for i in 0 to g_nof_streams - 1 generate gen_enable_sync_n : for i in 0 to g_nof_streams - 1 generate
-- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used) -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output
-- is forced to '1', so that for the disabled (= inactive = not used)
-- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low. -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
-- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share -- The purpose of being able to disable inactive signal inputs is that this avoids that one
-- the sync_n_combined to become unavailable (see gen_group_sync_n). -- inactive signal input will cause all signal inputs in a group that share the sync_n_combined
-- to become unavailable (see gen_group_sync_n).
-- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) or jesd204b_disable_arr(i); jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) or jesd204b_disable_arr(i);
...@@ -503,7 +525,9 @@ begin ...@@ -503,7 +525,9 @@ begin
-- Group the SYNC_N outputs -- Group the SYNC_N outputs
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
gen_group_sync_n : for i in 0 to g_nof_sync_n - 1 generate gen_group_sync_n : for i in 0 to g_nof_sync_n - 1 generate
jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group * i + c_nof_sync_n_per_group - 1 downto c_nof_sync_n_per_group * i)); jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(
c_nof_sync_n_per_group * i + c_nof_sync_n_per_group - 1 downto
c_nof_sync_n_per_group * i));
end generate; end generate;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
......
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