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5da47d1f · Job van Wee · 5ac50092 · 5da47d1f · 5ac50092 · 5da47d1f
Commit 5da47d1f authored May 2, 2022 by Job van Wee
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
 hdl_lib_name = lofar2_unb2c_ddrctrl
 hdl_library_clause_name = lofar2_unb2c_ddrctrl_lib
-hdl_lib_uses_synth = common technology mm unb2c_board 
+hdl_lib_uses_synth = common technology mm unb2c_board ddrctrl diag dp
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e2sg

--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl.sof.zip
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl.sof.zip
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/data/diag_sin_1024x18.hex
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/data/diag_sin_1024x18.hex
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/data/diag_sin_1024x8.hex
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/data/diag_sin_1024x8.hex
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--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/data/diag_sin_2048x18.hex
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/data/diag_sin_2048x18.hex
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
@@ -20,17 +20,18 @@
 --
 -------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, ddrctrl_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
-ENTITY unb2c_minimal IS
+ENTITY lofar2_unb2c_ddrctrl IS
  GENERIC (
-    g_design_name       : STRING  := "unb2c_minimal";
+    g_design_name       : STRING  := "lofar2_unb2c_ddrctrl";
    g_design_note       : STRING  := "UNUSED";
    g_technology        : NATURAL := c_tech_arria10_e2sg;
    g_sim               : BOOLEAN := FALSE; --Overridden by TB
@@ -62,15 +63,38 @@ ENTITY unb2c_minimal IS
    QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
  );
-END unb2c_minimal;
+END lofar2_unb2c_ddrctrl;
-ARCHITECTURE str OF unb2c_minimal IS
+ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
  -- Firmware version x.y
  -- If x >= 2, rom_info starts on 0x10000 and max size = 0x8192 words                                                                                
  CONSTANT c_fw_version             : t_unb2c_board_fw_version := (2, 0);
  CONSTANT c_mm_clk_freq            : NATURAL := c_unb2c_board_mm_clk_freq_125M;
+  CONSTANT c_bs_block_size          : NATURAL := 1024;
+  CONSTANT c_bs_bsn_w               : NATURAL := 64;
+  CONSTANT c_nof_streams            : NATURAL := 12;
+  CONSTANT c_data_w                 : NATURAL := 14;
+  -- wg_wideband_arr
+  CONSTANT c_wg_buf_directory       : STRING  := "data/";
+  CONSTANT c_wg_buf_dat_w           : NATURAL := 18; --default value of WG that fits 14 bits of ADC data
+  CONSTANT c_wg_buf_addr_w          : NATURAL := 10; --default value of WG for 1024 samples
+  CONSTANT c_bsn_nof_clk_per_sync   : NATURAL := sel_a_b(g_sim, 16*c_bs_block_size, c_sdp_N_clk_per_sync);
+  -- ddrctrl
+  CONSTANT c_tech_ddr               : t_c_tech_ddr          :=c_tech_ddr4_8g_1600m;
+  CONSTANT c_stop_percentage        : NATURAL               := 80;
+  -- diag_data_buffer
+  CONSTANT c_data_type              : t_diag_data_type_enum := e_data;
+  CONSTANT c_buf_nof_words          : NATURAL               := 1024;
+  -- diag_bsn_buffer
+  CONSTANT c_bsn_type               : t_diag_data_type_enum := e_real;
  -- System
  SIGNAL cs_sim                     : STD_LOGIC;
@@ -79,6 +103,7 @@ ARCHITECTURE str OF unb2c_minimal IS
  SIGNAL xo_rst_n                   : STD_LOGIC;
  SIGNAL mm_clk                     : STD_LOGIC;
  SIGNAL mm_rst                     : STD_LOGIC;
+  SIGNAL st_pps                     : STD_LOGIC;
  SIGNAL st_rst                     : STD_LOGIC;
  SIGNAL st_clk                     : STD_LOGIC;
@@ -144,7 +169,276 @@ ARCHITECTURE str OF unb2c_minimal IS
  SIGNAL qsfp_green_led_arr         : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
  SIGNAL qsfp_red_led_arr           : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+  -- bsn_source_v2
+  SIGNAL reg_bsn_source_v2_mosi     : t_mem_mosi;
+  SIGNAL reg_bsn_source_v2_miso     : t_mem_miso;
+  -- bsn_scheduler
+  SIGNAL reg_bsn_scheduler_wg_mosi  : t_mem_mosi;
+  SIGNAL reg_bsn_scheduler_wg_miso  : t_mem_miso;
+  SIGNAL trigger_wg                 : STD_LOGIC;
+  -- stop_in
+  SIGNAL  reg_stop_in_mosi          : t_mem_mosi;
+  SIGNAL  reg_stop_in_miso          : t_mem_miso;
+  SIGNAL  stop_in_arr               : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
+  -- ddrctrl
+  SIGNAL  st_sosi_arr               : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+  SIGNAL  out_siso                  : t_dp_siso;
+  SIGNAL  out_sosi_arr              : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+  SIGNAL  phy3_io                   : t_tech_ddr3_phy_io;
+  SIGNAL  phy3_ou                   : t_tech_ddr3_phy_ou;
+  SIGNAL  phy4_io                   : t_tech_ddr4_phy_io;
+  SIGNAL  phy4_ou                   : t_tech_ddr4_phy_ou;
+  -- data_buffer
+  SIGNAL  reg_data_buf_mosi         : t_mem_mosi;
+  SIGNAL  reg_data_buf_miso         : t_mem_miso;
+  SIGNAL  ram_data_buf_mosi         : t_mem_mosi;
+  SIGNAL  ram_data_buf_miso         : t_mem_miso;
+  SIGNAL  reg_rx_seq_data_mosi      : t_mem_mosi;
+  SIGNAL  reg_rx_seq_data_miso      : t_mem_miso;
+  SIGNAL  out_wr_data_ready_arr     : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
+  -- bsn_buffer
+  SIGNAL  reg_bsn_buf_mosi          : t_mem_mosi;
+  SIGNAL  reg_bsn_buf_miso          : t_mem_miso;
+  SIGNAL  ram_bsn_buf_mosi          : t_mem_mosi;
+  SIGNAL  ram_bsn_buf_miso          : t_mem_miso;
+  SIGNAL  reg_rx_seq_bsn_mosi       : t_mem_mosi;
+  SIGNAL  reg_rx_seq_bsn_miso       : t_mem_miso;
+  SIGNAL  out_wr_bsn_ready_arr      : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
+BEGIN
+  out_siso.ready        <= vector_or(out_wr_ready_arr) OR vector_or(out_wr_bsn_ready_arr);
+  FOR I IN 0 TO g_nof_streams-1 LOOP
+    out_sosi_arr(I).re  <= out_sosi_arr(I).bsn;
+  END LOOP;
+  u_bsn_source_v2 : ENTITY dp_lib.mms_dp_bsn_source_v2
+  GENERIC MAP (
+    g_cross_clock_domain     => TRUE,
+    g_block_size             => c_bs_block_size,
+    g_nof_clk_per_sync       => c_bsn_nof_clk_per_sync,
+    g_bsn_w                  => c_bs_bsn_w
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    dp_rst            => st_rst,
+    dp_clk            => st_clk,
+    dp_pps            => st_pps,
+    -- Memory-mapped clock domain
+    reg_mosi          => reg_bsn_source_v2_mosi,
+    reg_miso          => reg_bsn_source_v2_miso,
+    -- Streaming clock domain
+    bs_sosi           => bs_sosi,
+    bs_restart        => st_rst
+  );
+  u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
+  GENERIC MAP (
+    g_cross_clock_domain => TRUE,
+    g_bsn_w              => c_bs_bsn_w
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst      => mm_rst,
+    mm_clk      => mm_clk,
+    reg_mosi    => reg_bsn_scheduler_wg_mosi,
+    reg_miso    => reg_bsn_scheduler_wg_miso,
+    -- Streaming clock domain
+    dp_rst      => st_rst,
+    dp_clk      => st_clk,
+    snk_in      => bs_sosi,  -- only uses eop (= block sync), bsn[]
+    trigger_out => trigger_wg
+  );
+  u_wg_arr : ENTITY diag_lib.mms_diag_wg_wideband_arr
+  GENERIC MAP (
+    g_nof_streams        => c_nof_streams, 
+    g_cross_clock_domain => TRUE,
+    g_buf_dir            => c_wg_buf_directory,
+    -- Wideband parameters
+    g_wideband_factor    => 1, 
+    -- Basic WG parameters, see diag_wg.vhd for their meaning
+    g_buf_dat_w          => c_wg_buf_dat_w,
+    g_buf_addr_w         => c_wg_buf_addr_w,
+    g_calc_support       => TRUE,
+    g_calc_gain_w        => 1,
+    g_calc_dat_w         => c_sdp_W_adc
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst              => mm_rst,
+    mm_clk              => mm_clk,
+    reg_mosi            => reg_wg_mosi,
+    reg_miso            => reg_wg_miso,
+    buf_mosi            => ram_wg_mosi,
+    buf_miso            => ram_wg_miso,
+    -- Streaming clock domain
+    st_rst              => st_rst,
+    st_clk              => st_clk,
+    st_restart          => trigger_wg,
+    out_sosi_arr        => wg_sosi_arr
+  );
+  gen_concat : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
+    p_sosi : PROCESS(wg_sosi_arr(I), bs_sosi)
    BEGIN
+      st_sosi_arr(I)       <= bs_sosi;
+      st_sosi_arr(I).data  <= wg_sosi_arr(I).data;
+    END PROCESS;
+  END GENERATE;
+  u_stop_in_reg : ENTITY common_lib.mms_common_reg
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst              => mm_rst,
+    mm_clk              => mm_clk,
+    reg_mosi            => reg_stop_in_mosi,
+    reg_miso            => reg_stop_in_miso,
+    -- Streaming clock domain
+    st_rst              => st_rst,
+    st_clk              => st_clk,
+    in_reg              => stop_in_arr,
+    out_reg             => stop_in_arr
+  );
+END mms_common_reg;
+  u_ddrctrl : ENTITY ddrctrl_lib.ddrctrl
+  GENERIC MAP (
+    g_tech_ddr        => c_tech_ddr,
+    g_sim_model       => g_sim,
+    g_technology      => g_technology,
+    g_nof_streams     => c_nof_streams,
+    g_data_w          => c_data_w,
+    g_stop_percentage => c_stop_percentage,
+    g_block_size      => c_bs_block_size
+  )
+  PORT MAP (
+    clk               => st_clk,
+    rst               => st_rst,
+    mm_clk            => mm_clk,
+    mm_rst            => mm_rst,
+    in_sosi_arr       => st_sosi_arr,
+    stop_in           => stop_in_arr(0),
+    out_sosi_arr      => out_sosi_arr,
+    out_siso          => out_siso,
+    --PHY
+    phy3_io           => phy3_io,
+    phy3_ou           => phy3_ou,
+    phy4_io           => phy4_io,
+    phy4_ou           => phy4_ou
+  );
+  u_diag_data_buffer ENTITY diag.mms_diag_data_buffer_dev
+  GENERIC MAP (    
+    g_technology      => g_technology,
+    -- General
+    g_nof_streams     => c_nof_streams,
+    -- DB settings
+    g_data_type       => c_data_type,
+    g_data_w          => c_data_w,
+    g_buf_nof_data    => c_buf_nof_words,
+    g_buf_use_sync    => FALSE,
+    g_use_steps       => FALSE,
+    g_nof_steps       => c_diag_seq_rx_reg_nof_steps,
+    g_seq_dat_w       => c_data_w
+  );
+  PORT (
+    -- Memory-mapped clock domain
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    reg_data_buf_mosi => reg_data_buf_mosi,
+    reg_data_buf_miso => reg_data_buf_mosi,
+    ram_data_buf_mosi => ram_data_buf_mosi,
+    ram_data_buf_miso => ram_data_buf_mosi,
+    reg_rx_seq_mosi   => reg_rx_seq_data_mosi,
+    reg_rx_seq_miso   => reg_rx_seq_data_miso,
+    -- Streaming clock domain
+    dp_rst            => st_rst,
+    dp_clk            => st_clk,
+    in_sync           => sync,
+    in_sosi_arr       => out_sosi_arr
+    out_wr_done_arr   => out_wr_data_done_arr
+  );
+  u_diag_bsn_buffer ENTITY diag.mms_diag_data_buffer_dev
+  GENERIC MAP (    
+    g_technology      => g_technology,
+    -- General
+    g_nof_streams     => c_nof_streams,
+    -- DB settings
+    g_data_type       => c_bsn_type,
+    g_data_w          => t_dp_sosi.bsn'length,
+    g_buf_nof_data    => c_buf_nof_words,
+    g_buf_use_sync    => FALSE,
+    g_use_steps       => FALSE,
+    g_nof_steps       => c_diag_seq_rx_reg_nof_steps,
+    g_seq_dat_w       => c_data_w
+  );
+  PORT (
+    -- Memory-mapped clock domain
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    reg_data_buf_mosi => reg_bsn_buf_mosi,
+    reg_data_buf_miso => reg_bsn_buf_mosi,
+    ram_data_buf_mosi => ram_bsn_buf_mosi,
+    ram_data_buf_miso => ram_bsn_buf_mosi,
+    reg_rx_seq_mosi   => reg_rx_seq_bsn_mosi,
+    reg_rx_seq_miso   => reg_rx_seq_bsn_miso,
+    -- Streaming clock domain
+    dp_rst            => st_rst,
+    dp_clk            => st_clk,
+    in_sync           => sync,
+    in_sosi_arr       => out_sosi_arr
+    out_wr_done_arr   => out_wr_bsn_done_arr
+  );
  -----------------------------------------------------------------------------
  -- General control function
@@ -177,7 +471,7 @@ BEGIN
    dp_rst                   => st_rst,
    dp_clk                   => st_clk,
-    dp_pps                   => OPEN,
+    dp_pps                   => st_pps,
    dp_rst_in                => st_rst,
    dp_clk_in                => st_clk,
@@ -264,7 +558,7 @@ BEGIN
  -----------------------------------------------------------------------------
  -- MM master
  -----------------------------------------------------------------------------
-  u_mmm : ENTITY work.mmm_unb2c_minimal
+  u_mmm : ENTITY work.mmm_lofar2_unb2c_ddrctrl
  GENERIC MAP (
    g_sim         => g_sim,
    g_sim_unb_nr  => g_sim_unb_nr,
@@ -329,7 +623,42 @@ BEGIN
    -- Scrap RAM
    ram_scrap_mosi           => ram_scrap_mosi,
-    ram_scrap_miso           => ram_scrap_miso
+    ram_scrap_miso           => ram_scrap_miso,
+    -- bsn_source_v2
+    reg_bsn_source_v2_mosi   => reg_bsn_source_v2_mosi,
+    reg_bsn_source_v2_miso   => reg_bsn_source_v2_miso,
+    -- bsn_scheduler
+    reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+    reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+    -- wg_wideband_arr
+    reg_wg_mosi             => reg_wg_mosi,
+    reg_wg_miso             => reg_wg_miso,
+    ram_wg_mosi             => ram_wg_mosi,
+    ram_wg_miso             => ram_wg_miso,
+    -- stop_in
+    reg_stop_in_mosi        => reg_stop_in_mosi,
+    reg_stop_in_miso        => reg_stop_in_miso,
+    -- data_buffer
+    reg_data_buf_mosi       => reg_data_buf_mosi,
+    reg_data_buf_miso       => reg_data_buf_miso,
+    ram_data_buf_mosi       => ram_data_buf_mosi,
+    ram_data_buf_miso       => ram_data_buf_miso,
+    reg_rx_seq_data_mosi    => reg_rx_seq_data_mosi,
+    reg_rx_seq_data_miso    => reg_rx_seq_data_miso,
+    -- bsn_buffer
+    reg_bsn_buf_mosi        => reg_bsn_buf_mosi,
+    reg_bsn_buf_miso        => reg_bsn_buf_miso,
+    ram_bsn_buf_mosi        => ram_bsn_buf_mosi,
+    ram_bsn_buf_miso        => ram_bsn_buf_miso,
+    reg_rx_seq_bsn_mosi     => reg_rx_seq_bsn_mosi,
+    reg_rx_seq_bsn_miso     => reg_rx_seq_bsn_miso
  );
  u_front_led : ENTITY unb2c_board_lib.unb2c_board_qsfp_leds

--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
@@ -28,10 +28,10 @@ USE unb2c_board_lib.unb2c_board_pkg.ALL;
 USE unb2c_board_lib.unb2c_board_peripherals_pkg.ALL;
 USE mm_lib.mm_file_pkg.ALL;
 USE mm_lib.mm_file_unb_pkg.ALL;
-USE work.qsys_unb2c_minimal_pkg.ALL;
+USE work.qsys_lofar2_unb2c_ddrctrl_pkg.ALL;
-ENTITY mmm_unb2c_minimal IS
+ENTITY mmm_lofar2_unb2c_ddrctrl IS
  GENERIC (
    g_sim         : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
    g_sim_unb_nr  : NATURAL := 0;
@@ -94,11 +94,50 @@ ENTITY mmm_unb2c_minimal IS
    -- Scrap RAM
    ram_scrap_mosi            : OUT t_mem_mosi;  
-    ram_scrap_miso           : IN  t_mem_miso
+    ram_scrap_miso            : IN  t_mem_miso;
+    -- bsn_source_v2
+    reg_bsn_source_v2_mosi    : OUT t_mem_mosi; 
+    reg_bsn_source_v2_miso    : IN  t_mem_miso;
+    -- bsn_sceduler
+    reg_bsn_scheduler_wg_mosi : OUT t_mem_mosi;
+    reg_bsn_scheduler_wg_miso : IN  t_mem_miso;
+    -- wg_wideband_arr
+    reg_wg_mosi               : OUT t_mem_mosi;
+    reg_wg_miso               : IN  t_mem_miso;
+    ram_wg_mosi               : OUT t_mem_mosi;
+    ram_wg_miso               : IN  t_mem_miso;
+    -- stop_in
+    reg_stop_in_mosi          : OUT t_mem_mosi;
+    reg_stop_in_miso          : IN  t_mem_miso;
+    -- data_buffer
+    reg_data_buf_mosi         : OUT t_mem_mosi;
+    reg_data_buf_miso         : IN  t_mem_miso;
+    ram_data_buf_mosi         : OUT t_mem_mosi;
+    ram_data_buf_miso         : IN  t_mem_miso;
+    reg_rx_seq_data_mosi      : OUT t_mem_mosi;
+    reg_rx_seq_data_miso      : IN  t_mem_miso;
+    -- bsn_buffer
+    reg_bsn_buf_mosi          : OUT t_mem_mosi;
+    reg_bsn_buf_miso          : IN  t_mem_miso;
+    ram_bsn_buf_mosi          : OUT t_mem_mosi;
+    ram_bsn_buf_miso          : IN  t_mem_miso;
+    reg_rx_seq_bsn_mosi       : OUT t_mem_mosi;
+    reg_rx_seq_bsn_miso       : IN  t_mem_miso;
 );
-END mmm_unb2c_minimal;
+END mmm_lofar2_unb2c_ddrctrl;
-ARCHITECTURE str OF mmm_unb2c_minimal IS
+ARCHITECTURE str OF mmm_lofar2_unb2c_ddrctrl IS
  CONSTANT c_sim_node_nr   : NATURAL := g_sim_node_nr;
  CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
@@ -137,6 +176,42 @@ BEGIN
    u_mm_file_reg_eth             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
                                               PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+    u_mm_file_reg_bsn_source_v2   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
+                                               PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
+    u_mm_file_reg_bsn_scheduler   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+                                               PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_wg_mosi, reg_bsn_scheduler_wg_miso );
+    u_mm_file_reg_wg_wideband_arr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG_WIDEBAND_ARR")
+                                               PORT MAP(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso);
+    u_mm_file_ram_wg_wideband_arr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG_WIDEBAND_ARR")
+                                               PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso);
+    u_mm_file_reg_stop_in         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STOP_IN")
+                                               PORT MAP(mm_rst, mm_clk, reg_stop_in_mosi, reg_stop_in_miso);
+    u_mm_file_reg_data_buf        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DATA_BUF")
+                                               PORT MAP(mm_rst, mm_clk, reg_data_buf_mosi, reg_data_buf_miso);
+    u_mm_file_ram_data_buf        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DATA_BUF")
+                                               PORT MAP(mm_rst, mm_clk, ram_data_buf_mosi, ram_data_buf_miso);
+    u_mm_file_reg_rx_seq_data     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_DATA")
+                                               PORT MAP(mm_rst, mm_clk, reg_rx_seq_data_mosi, reg_rx_seq_data_miso);
+    u_mm_file_reg_bsn_buf         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_BUF")
+                                               PORT MAP(mm_rst, mm_clk, reg_bsn_buf_mosi, reg_bsn_buf_miso);
+    u_mm_file_ram_bsn_buf         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BSN_BUF")
+                                               PORT MAP(mm_rst, mm_clk, ram_bsn_buf_mosi, ram_bsn_buf_miso);
+    u_mm_file_reg_rx_seq_bsn      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_BSN")
+                                               PORT MAP(mm_rst, mm_clk, reg_rx_seq_bsn_mosi, reg_rx_seq_bsn_miso);
    ----------------------------------------------------------------------------
    -- Procedure that polls a sim control file that can be used to e.g. get
    -- the simulation time in ns
@@ -151,7 +226,7 @@ BEGIN
  -- QSYS for synthesis
  ----------------------------------------------------------------------------
  gen_qsys : IF g_sim = FALSE GENERATE
-    u_qsys : qsys_unb2c_minimal
+    u_qsys : qsys_lofar2_unb2c_ddrctrl
    PORT MAP (
      clk_clk                                   => mm_clk,

--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
@@ -22,13 +22,13 @@
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
-PACKAGE qsys_unb2c_minimal_pkg IS
+PACKAGE qsys_lofar2_unb2c_ddrctrl_pkg IS
    ----------------------------------------------------------------------
    -- this component declaration is copy-pasted from Quartus QSYS builder
    ----------------------------------------------------------------------
-    component qsys_unb2c_minimal is
+    component qsys_lofar2_unb2c_ddrctrl is
        port (
            avs_eth_0_reset_export                 : out std_logic;                                        -- export
            avs_eth_0_clk_export                   : out std_logic;                                        -- export
@@ -144,6 +144,6 @@ PACKAGE qsys_unb2c_minimal_pkg IS
            rom_system_info_read_export            : out std_logic;                                        -- export
            rom_system_info_readdata_export        : in  std_logic_vector(31 downto 0) := (others => 'X')  -- export
        );
-    end component qsys_unb2c_minimal;
+    end component qsys_lofar2_unb2c_ddrctrl;
-END qsys_unb2c_minimal_pkg;
+END qsys_lofar2_unb2c_ddrctrl_pkg;
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -20,7 +20,7 @@
 --
 -------------------------------------------------------------------------------
-- Purpose: Test bench for unb2c_minimal.
+-- Purpose: Test bench for lofar2_unb2c_ddrctrl.
 -- Description:
 --   The DUT can be targeted at unb 0, node 3 with the same Python scripts 
 --   that are used on hardware. 
@@ -29,10 +29,10 @@
 --     > run_modelsim & (to start Modeslim)
 --
 --   In Modelsim do:
--     > lp unb2c_minimal
+--     > lp lofar2_unb2c_ddrctrl
 --     > mk clean all (only first time to clean all libraries)
--     > mk all (to compile all libraries that are needed for unb2c_minimal)
+--     > mk all (to compile all libraries that are needed for lofar2_unb2c_ddrctrl)
--     . load tb_unb1_minimal simulation by double clicking the tb_unb2c_minimal icon
+--     . load tb_unb1_minimal simulation by double clicking the tb_lofar2_unb2c_ddrctrl icon
 --     > as 10 (to view signals in Wave Window)
 --     > run 100 us (or run -all)
 --
@@ -50,15 +50,15 @@ USE common_lib.tb_common_pkg.ALL;
 USE i2c_lib.i2c_dev_unb2_pkg.ALL;
 USE i2c_lib.i2c_commander_unb2_pmbus_pkg.ALL;
-ENTITY tb_unb2c_minimal IS
+ENTITY tb_lofar2_unb2c_ddrctrl IS
    GENERIC (
-      g_design_name : STRING  := "unb2c_minimal";
+      g_design_name : STRING  := "lofar2_unb2c_ddrctrl";
      g_sim_unb_nr  : NATURAL := 0; -- UniBoard 0
      g_sim_node_nr : NATURAL := 3  -- Node 3
    );
-END tb_unb2c_minimal;
+END tb_lofar2_unb2c_ddrctrl;
-ARCHITECTURE tb OF tb_unb2c_minimal IS
+ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
  CONSTANT c_sim             : BOOLEAN := TRUE;
@@ -120,7 +120,7 @@ BEGIN
  ------------------------------------------------------------------------------
  -- DUT
  ------------------------------------------------------------------------------
-  u_unb2c_minimal : ENTITY work.unb2c_minimal
+  u_lofar2_unb2c_ddrctrl : ENTITY work.lofar2_unb2c_ddrctrl
    GENERIC MAP (
      g_sim         => c_sim,
      g_sim_unb_nr  => c_unb_nr,

--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
--- a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
@@ -96,7 +96,8 @@ ENTITY diag_data_buffer_dev IS
    in_data      : IN  STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
    in_sync      : IN  STD_LOGIC := '0';
-    in_val       : IN  STD_LOGIC  
+    in_val       : IN  STD_LOGIC;
+    out_wr_done  : OUT STD_LOGIC := '1'  
  );
 END diag_data_buffer_dev;
@@ -168,6 +169,8 @@ BEGIN
  ASSERT c_mm_factor=2**true_log2(c_mm_factor) REPORT "Only support mixed width data that uses a power of 2 multiple." SEVERITY FAILURE;
+  out_wr_done <= wr_done;  
  ram_mm_miso <= i_ram_mm_miso;
  rd_last <= '1' WHEN UNSIGNED(ram_mm_mosi.address(c_buf_mm.adr_w-1 DOWNTO 0))=c_nof_data_mm-1 AND ram_mm_mosi.rd='1' ELSE '0';

--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
@@ -102,7 +102,8 @@ ENTITY mms_diag_data_buffer_dev IS
    -- ST interface
    in_sync           : IN  STD_LOGIC := '0';  -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
-    in_sosi_arr       : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
+    in_sosi_arr       : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+    out_wr_done_arr   : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
  );
 END mms_diag_data_buffer_dev;
@@ -187,7 +188,8 @@ BEGIN
        in_data     => in_data_arr(I),
        in_sync     => in_sync,
-        in_val      => in_sosi_arr(I).valid
+        in_val      => in_sosi_arr(I).valid,
+        out_wr_done => out_wr_done_arr(I)
      );
    END GENERATE;
  END GENERATE;