initial commit of new design for ddrctrl

applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg

+hdl_lib_name = lofar2_unb2c_ddrctrl
+hdl_library_clause_name = lofar2_unb2c_ddrctrl_lib
+hdl_lib_uses_synth = common technology mm unb2c_board 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
+    src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
+    src/vhdl/lofar2_unb2c_ddrctrl.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+
+regression_test_vhdl =
+    tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+
+[modelsim_project_file]
+modelsim_copy_files = 
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+    quartus .
+
+quartus_qsf_files =
+    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+    quartus/lofar2_unb2c_ddrctrl_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl.qip
+
+quartus_ip_files =
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_avs2_eth_coe_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_scrap.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_timer_0.ip
+
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+

applications/lofar2/designs/lofar2_unb2c_ddrctrl/lofar2_unb2c_ddrctrl.fpga.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : fpga
+
+hdl_library_name: lofar2_unb2c_ddrctrl
+fpga_name       : lofar2_unb2c_ddrctrl
+fpga_description: "FPGA design lofar2_unb2c_ddrctrl"
+
+peripherals:
+  #############################################################################
+  # Factory / minimal (from ctrl_unb2c_board.vhd)
+  #############################################################################
+  - peripheral_name: unb2c_board/system_info
+    lock_base_address: 0x10000
+    mm_port_names:
+      - ROM_SYSTEM_INFO
+      - PIO_SYSTEM_INFO
+
+  - peripheral_name: unb2c_board/wdi
+    mm_port_names:
+      - REG_WDI
+
+  - peripheral_name: unb2c_board/unb2_fpga_sens
+    mm_port_names:
+      - REG_FPGA_TEMP_SENS
+      - REG_FPGA_VOLTAGE_SENS
+
+  - peripheral_name: unb2c_board/ram_scrap
+    mm_port_names:
+      - RAM_SCRAP
+
+  - peripheral_name: eth/eth
+    mm_port_names:
+      - AVS_ETH_0_TSE
+      - AVS_ETH_0_REG
+      - AVS_ETH_0_RAM
+      
+  - peripheral_name: ppsh/ppsh
+    mm_port_names:
+      - PIO_PPS
+      
+  - peripheral_name: epcs/epcs
+    mm_port_names:
+      - REG_EPCS
+
+  - peripheral_name: dp/dpmm
+    mm_port_names:
+      - REG_DPMM_CTRL
+      - REG_DPMM_DATA
+
+  - peripheral_name: dp/mmdp
+    mm_port_names:
+      - REG_MMDP_CTRL
+      - REG_MMDP_DATA
+
+  - peripheral_name: remu/remu
+    mm_port_names:
+      - REG_REMU
+