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RTSD
HDL
Commits
5d7dee5f
Commit
5d7dee5f
authored
10 years ago
by
Zanting
Browse files
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Plain Diff
Fixed memory address widths
parent
9806287b
Branches
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applications/unb1_reorder/quartus/sopc_unb1_reorder.sopc
+54
-54
54 additions, 54 deletions
applications/unb1_reorder/quartus/sopc_unb1_reorder.sopc
with
54 additions
and
54 deletions
applications/unb1_reorder/quartus/sopc_unb1_reorder.sopc
+
54
−
54
View file @
5d7dee5f
...
@@ -84,23 +84,7 @@
...
@@ -84,23 +84,7 @@
type = "String";
type = "String";
}
}
}
}
element pio_pps.mem
element pio_system_info.mem
{
datum baseAddress
{
value = "728";
type = "long";
}
}
element reg_diag_data_buffer_re.mem
{
datum baseAddress
{
value = "256";
type = "long";
}
}
element rom_system_info.mem
{
{
datum _lockedAddress
datum _lockedAddress
{
{
...
@@ -109,7 +93,7 @@
...
@@ -109,7 +93,7 @@
}
}
datum baseAddress
datum baseAddress
{
{
value = "
4096
";
value = "
0
";
type = "long";
type = "long";
}
}
}
}
...
@@ -126,48 +110,56 @@
...
@@ -126,48 +110,56 @@
type = "long";
type = "long";
}
}
}
}
element r
am
_diag_data_buffer_
im
.mem
element r
eg
_diag_data_buffer_
re
.mem
{
{
datum baseAddress
datum baseAddress
{
{
value = "26
2144
";
value = "2
5
6";
type = "long";
type = "long";
}
}
}
}
element r
am
_diag_data_buffer_
re
.mem
element r
eg
_diag_data_buffer_
im
.mem
{
{
datum baseAddress
datum baseAddress
{
{
value = "
393216
";
value = "
128
";
type = "long";
type = "long";
}
}
}
}
element ram_diag_bg.mem
element rom_system_info.mem
{
datum _lockedAddress
{
{
value = "1";
type = "boolean";
}
datum baseAddress
datum baseAddress
{
{
value = "
16384
";
value = "
4096
";
type = "long";
type = "long";
}
}
}
}
element pio_
system_info
.mem
element pio_
pps
.mem
{
{
datum
_locked
Address
datum
base
Address
{
{
value = "1";
value = "728";
type = "boolean";
type = "long";
}
}
}
element ram_diag_data_buffer_im.mem
{
datum baseAddress
datum baseAddress
{
{
value = "
0
";
value = "
262144
";
type = "long";
type = "long";
}
}
}
}
element r
eg
_diag_data_buffer_
im
.mem
element r
am
_diag_data_buffer_
re
.mem
{
{
datum baseAddress
datum baseAddress
{
{
value = "
128
";
value = "
393216
";
type = "long";
type = "long";
}
}
}
}
...
@@ -187,19 +179,27 @@
...
@@ -187,19 +179,27 @@
type = "long";
type = "long";
}
}
}
}
element reg_unb_sens.mem
{
datum baseAddress
{
value = "608";
type = "long";
}
}
element ram_ss_ss_wide.mem
element ram_ss_ss_wide.mem
{
{
datum baseAddress
datum baseAddress
{
{
value = "
52428
8";
value = "
3276
8";
type = "long";
type = "long";
}
}
}
}
element r
eg_unb_sens
.mem
element r
am_diag_bg
.mem
{
{
datum baseAddress
datum baseAddress
{
{
value = "
60
8";
value = "
52428
8";
type = "long";
type = "long";
}
}
}
}
...
@@ -207,7 +207,7 @@
...
@@ -207,7 +207,7 @@
{
{
datum baseAddress
datum baseAddress
{
{
value = "
32768
";
value = "
16384
";
type = "long";
type = "long";
}
}
}
}
...
@@ -378,19 +378,24 @@
...
@@ -378,19 +378,24 @@
type = "int";
type = "int";
}
}
}
}
element
pio_wdi
.s1
element
timer_0
.s1
{
{
datum baseAddress
datum baseAddress
{
{
value = "
704
";
value = "
576
";
type = "long";
type = "long";
}
}
}
}
element timer_0.s1
element onchip_memory2_0.s1
{
datum _lockedAddress
{
{
value = "1";
type = "boolean";
}
datum baseAddress
datum baseAddress
{
{
value = "
576
";
value = "
131072
";
type = "long";
type = "long";
}
}
}
}
...
@@ -402,16 +407,11 @@
...
@@ -402,16 +407,11 @@
type = "long";
type = "long";
}
}
}
}
element onchip_memory2_0.s1
element pio_wdi.s1
{
datum _lockedAddress
{
{
value = "1";
type = "boolean";
}
datum baseAddress
datum baseAddress
{
{
value = "
131072
";
value = "
704
";
type = "long";
type = "long";
}
}
}
}
...
@@ -440,8 +440,8 @@
...
@@ -440,8 +440,8 @@
<parameter
name=
"maxAdditionalLatency"
value=
"0"
/>
<parameter
name=
"maxAdditionalLatency"
value=
"0"
/>
<parameter
name=
"projectName"
value=
"unb1_reorder.qpf"
/>
<parameter
name=
"projectName"
value=
"unb1_reorder.qpf"
/>
<parameter
name=
"sopcBorderPoints"
value=
"true"
/>
<parameter
name=
"sopcBorderPoints"
value=
"true"
/>
<parameter
name=
"systemHash"
value=
"-4
19780
264
05
"
/>
<parameter
name=
"systemHash"
value=
"-4
29159
264
88
"
/>
<parameter
name=
"timeStamp"
value=
"142710
5050254
"
/>
<parameter
name=
"timeStamp"
value=
"142710
7370112
"
/>
<parameter
name=
"useTestBenchNamingPattern"
value=
"false"
/>
<parameter
name=
"useTestBenchNamingPattern"
value=
"false"
/>
<module
kind=
"clock_source"
version=
"11.1"
enabled=
"1"
name=
"clk_0"
>
<module
kind=
"clock_source"
version=
"11.1"
enabled=
"1"
name=
"clk_0"
>
<parameter
name=
"clockFrequency"
value=
"25000000"
/>
<parameter
name=
"clockFrequency"
value=
"25000000"
/>
...
@@ -542,7 +542,7 @@
...
@@ -542,7 +542,7 @@
<parameter
name=
"dcache_numTCDM"
value=
"_0"
/>
<parameter
name=
"dcache_numTCDM"
value=
"_0"
/>
<parameter
name=
"dcache_lineSize"
value=
"_32"
/>
<parameter
name=
"dcache_lineSize"
value=
"_32"
/>
<parameter
name=
"dcache_bursts"
value=
"false"
/>
<parameter
name=
"dcache_bursts"
value=
"false"
/>
<parameter
name=
"dataSlaveMapParam"
>
<![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_im.mem' start='0x80' end='0x100' /><slave name='reg_diag_data_buffer_re.mem' start='0x100' end='0x180' /><slave name='reg_bsn_monitor.mem' start='0x180' end='0x200' /><slave name='avs_eth_0.mms_reg' start='0x200' end='0x240' /><slave name='timer_0.s1' start='0x240' end='0x260' /><slave name='reg_unb_sens.mem' start='0x260' end='0x280' /><slave name='reg_diag_bg.mem' start='0x280' end='0x2A0' /><slave name='altpll_0.pll_slave' start='0x2A0' end='0x2B0' /><slave name='pio_debug_wave.s1' start='0x2B0' end='0x2C0' /><slave name='pio_wdi.s1' start='0x2C0' end='0x2D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2D0' end='0x2D8' /><slave name='pio_pps.mem' start='0x2D8' end='0x2E0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='
ram_diag_bg.me
m' start='0x4000' end='0x
8
000' /><slave name='
avs_eth_0.mms_ra
m' start='0x8000' end='0x
9
000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buffer_im.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_data_buffer_re.mem' start='0x60000' end='0x80000' /><slave name='ram_
ss_ss_wide
.mem' start='0x80000' end='0xA0000' /></address-map>]]>
</parameter>
<parameter
name=
"dataSlaveMapParam"
>
<![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_im.mem' start='0x80' end='0x100' /><slave name='reg_diag_data_buffer_re.mem' start='0x100' end='0x180' /><slave name='reg_bsn_monitor.mem' start='0x180' end='0x200' /><slave name='avs_eth_0.mms_reg' start='0x200' end='0x240' /><slave name='timer_0.s1' start='0x240' end='0x260' /><slave name='reg_unb_sens.mem' start='0x260' end='0x280' /><slave name='reg_diag_bg.mem' start='0x280' end='0x2A0' /><slave name='altpll_0.pll_slave' start='0x2A0' end='0x2B0' /><slave name='pio_debug_wave.s1' start='0x2B0' end='0x2C0' /><slave name='pio_wdi.s1' start='0x2C0' end='0x2D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2D0' end='0x2D8' /><slave name='pio_pps.mem' start='0x2D8' end='0x2E0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='
avs_eth_0.mms_ra
m' start='0x4000' end='0x
5
000' /><slave name='
ram_ss_ss_wide.me
m' start='0x8000' end='0x
10
000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buffer_im.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_data_buffer_re.mem' start='0x60000' end='0x80000' /><slave name='ram_
diag_bg
.mem' start='0x80000' end='0xA0000' /></address-map>]]>
</parameter>
<parameter
name=
"dataAddrWidth"
value=
"20"
/>
<parameter
name=
"dataAddrWidth"
value=
"20"
/>
<parameter
name=
"customInstSlavesSystemInfo"
value=
"<info/>"
/>
<parameter
name=
"customInstSlavesSystemInfo"
value=
"<info/>"
/>
<parameter
name=
"cpuReset"
value=
"false"
/>
<parameter
name=
"cpuReset"
value=
"false"
/>
...
@@ -872,12 +872,12 @@ q]]></parameter>
...
@@ -872,12 +872,12 @@ q]]></parameter>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
</module>
</module>
<module
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"ram_diag_bg"
>
<module
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"ram_diag_bg"
>
<parameter
name=
"g_adr_w"
value=
"1
2
"
/>
<parameter
name=
"g_adr_w"
value=
"1
5
"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
</module>
</module>
<module
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"ram_ss_ss_wide"
>
<module
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"ram_ss_ss_wide"
>
<parameter
name=
"g_adr_w"
value=
"1
5
"
/>
<parameter
name=
"g_adr_w"
value=
"1
3
"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
</module>
</module>
...
@@ -1123,7 +1123,7 @@ q]]></parameter>
...
@@ -1123,7 +1123,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
start=
"cpu_0.data_master"
end=
"ram_diag_bg.mem"
>
end=
"ram_diag_bg.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x
4
000"
/>
<parameter
name=
"baseAddress"
value=
"0x
00080
000"
/>
</connection>
</connection>
<connection
<connection
kind=
"clock"
kind=
"clock"
...
@@ -1136,7 +1136,7 @@ q]]></parameter>
...
@@ -1136,7 +1136,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
start=
"cpu_0.data_master"
end=
"ram_ss_ss_wide.mem"
>
end=
"ram_ss_ss_wide.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x
00080
000"
/>
<parameter
name=
"baseAddress"
value=
"0x
8
000"
/>
</connection>
</connection>
<connection
<connection
kind=
"clock"
kind=
"clock"
...
@@ -1174,7 +1174,7 @@ q]]></parameter>
...
@@ -1174,7 +1174,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
start=
"cpu_0.data_master"
end=
"avs_eth_0.mms_ram"
>
end=
"avs_eth_0.mms_ram"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x
8
000"
/>
<parameter
name=
"baseAddress"
value=
"0x
4
000"
/>
</connection>
</connection>
<connection
<connection
kind=
"interrupt"
kind=
"interrupt"
...
...
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