Add debug signals. Correct single cycle rxlink_sysref. Correct FIFO data width...

Add debug signals. Correct single cycle rxlink_sysref. Correct FIFO data width to c_jesd204b_rx_framer_data_w.

libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd

@@ -26,7 +26,7 @@
 -- Description
 --   Currently only 12 streams because of the 12 channel reset block
 --   The sync_n signals are gated together to form g_nof_sync_n outputs
---
+-- . v2 uses FIFO in IP to get from rxlink_clk at 100 MHz to dp_clk at 200 MHz
 
 library IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e2sg_jesd204b_lib;
 use IEEE.std_logic_1164.all;
@@ -128,15 +128,25 @@ architecture str of ip_arria10_e2sg_jesd204b_v2 is
   signal mm_core_pll_locked         : std_logic;
   signal rxlink_sysref_1            : std_logic;
   signal rxlink_sysref_2            : std_logic;
-  signal rxframe_sysref_1           : std_logic;
-  signal rxframe_sysref_2           : std_logic;
+  signal rxlink_sysref_3            : std_logic;
+  signal rxlink_sysref              : std_logic;  -- single rxlink_clk cycle pulse
 
   -- Data path
   signal jesd204b_rx_link_data_arr  : std_logic_vector(c_jesd204b_rx_data_w * g_nof_streams - 1 downto 0);
   signal jesd204b_rx_link_valid_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+  signal jesd204b_rx_link_somf_arr  : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0);
+
+  -- debug signal to view input 0 in Wave Window
+  signal jesd204b_rx_link_data      : std_logic_vector(c_jesd204b_rx_data_w - 1 downto 0);
+  signal jesd204b_rx_link_data_hi   : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  signal jesd204b_rx_link_data_lo   : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  signal jesd204b_rx_link_valid     : std_logic;
+  signal jesd204b_rx_link_somf      : std_logic_vector(c_jesd204b_rx_somf_w - 1 downto 0);
+  signal jesd204b_rx_link_somf_hi   : std_logic_vector(c_jesd204b_rx_framer_somf_w - 1 downto 0);
+  signal jesd204b_rx_link_somf_lo   : std_logic_vector(c_jesd204b_rx_framer_somf_w - 1 downto 0);
+
   signal rxlink_valid               : std_logic;
-  signal jesd204b_rx_somf_arr       : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0);
-  signal rxlink_sosi_arr            : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+  signal rxlink_sosi_arr            : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
   signal dplink_sosi_arr            : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
   signal dplink_siso_arr            : t_dp_siso_arr(g_nof_streams - 1 downto 0);
   signal fifo_state                 : t_fifo_state_enum;
@@ -144,6 +154,18 @@ architecture str of ip_arria10_e2sg_jesd204b_v2 is
   signal dp_toggle                  : std_logic := '0';
   signal dp_valid                   : std_logic := '0';
 
+  -- debug signal to view input 0 in Wave Window
+  signal rxlink_sosi                : t_dp_sosi;
+  signal rxlink_data                : std_logic_vector(c_jesd204b_rx_data_w - 1 downto 0);
+  signal rxlink_data_hi             : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  signal rxlink_data_lo             : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  signal dplink_sosi                : t_dp_sosi;
+  signal dplink_data                : std_logic_vector(c_jesd204b_rx_data_w - 1 downto 0);
+  signal dplink_data_hi             : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  signal dplink_data_lo             : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  signal i_dp_sosi_arr              : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+  signal dp_sosi                    : t_dp_sosi;
+
   -- outputs to control ADC initialization/syncronization phase
   signal jesd204b_sync_n_internal_arr   : std_logic_vector(g_nof_streams - 1 downto 0);
   signal jesd204b_sync_n_enabled_arr    : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -249,6 +271,27 @@ architecture str of ip_arria10_e2sg_jesd204b_v2 is
     );
   end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
 begin
+  -- Debug signals to view input 0 in Wave Window
+  jesd204b_rx_link_data <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w - 1 downto 0);
+  jesd204b_rx_link_data_hi <= jesd204b_rx_link_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
+  jesd204b_rx_link_data_lo <= jesd204b_rx_link_data(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  jesd204b_rx_link_valid <= jesd204b_rx_link_valid_arr(0);
+  jesd204b_rx_link_somf <= jesd204b_rx_link_somf_arr(c_jesd204b_rx_somf_w - 1 downto 0);
+  jesd204b_rx_link_somf_hi <= jesd204b_rx_link_somf(c_jesd204b_rx_somf_w - 1 downto c_jesd204b_rx_framer_somf_w);
+  jesd204b_rx_link_somf_lo <= jesd204b_rx_link_somf(c_jesd204b_rx_framer_somf_w - 1 downto 0);
+
+  rxlink_sosi <= rxlink_sosi_arr(0);
+  rxlink_data <= rxlink_sosi.data(c_jesd204b_rx_data_w - 1 downto 0);
+  rxlink_data_hi <= rxlink_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
+  rxlink_data_lo <= rxlink_data(c_jesd204b_rx_framer_data_w - 1 downto 0);
+
+  dplink_sosi <= dplink_sosi_arr(0);
+  dplink_data <= dplink_sosi.data(c_jesd204b_rx_data_w - 1 downto 0);
+  dplink_data_hi <= dplink_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
+  dplink_data_lo <= dplink_data(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  dp_sosi_arr <= i_dp_sosi_arr;
+  dp_sosi <= i_dp_sosi_arr(0);
+
   -- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
   -- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e2sg_jesd204b.
 
@@ -317,9 +360,9 @@ begin
           rxlink_rst_n_reset_n       => rxlink_rst_n_arr(i),  -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
           rxphy_clk                  => OPEN,  -- Not used in Subclass 0 (Intel JESD204B-UG p63)
           sof                        => OPEN,
-          somf                       => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1
-                                                      downto c_jesd204b_rx_somf_w * i),
-          sysref                     => rxlink_sysref_2
+          somf                       => jesd204b_rx_link_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1
+                                                           downto c_jesd204b_rx_somf_w * i),
+          sysref                     => rxlink_sysref
         );
 
         -- Group jesd204b_rx_link data, valid and sync (= sysref) into rxlink_sosi_arr,
@@ -327,7 +370,7 @@ begin
         rxlink_sosi_arr(i).data <= RESIZE_DP_DATA(jesd204b_rx_link_data_arr
                                                   (i * c_jesd204b_rx_data_w + c_jesd204b_rx_data_w - 1 downto
                                                    i * c_jesd204b_rx_data_w));
-        rxlink_sosi_arr(i).sync <= rxlink_sysref_2;
+        rxlink_sosi_arr(i).sync <= rxlink_sysref;
         rxlink_sosi_arr(i).valid <= rxlink_valid;
 
         -- One cycle rd-rdval latency, waitrequest = '0' fixed
@@ -416,19 +459,19 @@ begin
       begin
         if rising_edge(dp_clk) then
           if dp_valid = '0' then
-            dp_sosi_arr(i) <= c_dp_sosi_rst;  -- Force all to 0 when Rx JESD204B has stopped
+            i_dp_sosi_arr(i) <= c_dp_sosi_rst;  -- Force all to 0 when Rx JESD204B has stopped
           else
-            dp_sosi_arr(i).valid <= '1';
+            i_dp_sosi_arr(i).valid <= '1';
             if dp_toggle = '1' then
-              dp_sosi_arr(i).sync <= dplink_sosi_arr(i).sync;
-              dp_sosi_arr(i).data <= RESIZE_DP_SDATA(dplink_sosi_arr(i).data(
-                                     c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
-                                     c_jesd204b_rx_data_w * i));
+              i_dp_sosi_arr(i).sync <= dplink_sosi_arr(i).sync;
+              i_dp_sosi_arr(i).data <= RESIZE_DP_SDATA(dplink_sosi_arr(i).data(
+                                       c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
+                                       c_jesd204b_rx_data_w * i));
             else
-              dp_sosi_arr(i).sync <= '0';
-              dp_sosi_arr(i).data <= RESIZE_DP_SDATA(dplink_sosi_arr(i).data(
-                                     c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
-                                     c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w));
+              i_dp_sosi_arr(i).sync <= '0';
+              i_dp_sosi_arr(i).data <= RESIZE_DP_SDATA(dplink_sosi_arr(i).data(
+                                       c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
+                                       c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w));
             end if;
           end if;
         end if;
@@ -450,10 +493,10 @@ begin
     u_dp_fifo_dc_arr : entity dp_lib.dp_fifo_dc_arr
       generic map (
         g_nof_streams    => g_nof_streams,
-        g_data_w         => c_jesd204b_rx_framer_data_w,  -- 16b
-        g_data_signed    => true,
+        g_data_w         => c_jesd204b_rx_data_w,  -- 32b
+        g_data_signed    => false,
         g_use_sync       => true,
-        g_use_channel    => false,  -- no need to pass on jesd204b_rx_somf_arr
+        g_use_channel    => false,  -- no need to pass on jesd204b_rx_link_somf_arr
         g_fifo_size      => c_fifo_size
       )
       port map (
@@ -511,14 +554,19 @@ begin
       if core_pll_locked = '0' then
         rxlink_sysref_1 <= '0';
         rxlink_sysref_2 <= '0';
+        rxlink_sysref_3 <= '0';
         jesd204b_sync_n_arr <= (others => '0');
       elsif rising_edge(rxlink_clk) then
         rxlink_sysref_1 <= jesd204b_sysref;
         rxlink_sysref_2 <= rxlink_sysref_1;
+        rxlink_sysref_3 <= rxlink_sysref_2;
         jesd204b_sync_n_arr <= jesd204b_sync_n_combined_arr;
       end if;
     end process;
 
+    -- Make single rxlink_clk cycle pulse of rxlink_sysref_2
+    rxlink_sysref <= rxlink_sysref_2 and not rxlink_sysref_3;
+
     -- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
     gen_jesd204b_rx_corepll_freqsel : if g_jesd_freq = "200MHz" generate
       u_ip_arria10_e2sg_jesd204b_rx_corepll_200MHz : ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz