Added reg_io_ddr to the io_ddr entity

applications/unb1_reorder/src/vhdl/mmm_unb1_reorder.vhd

@@ -111,7 +111,11 @@ ENTITY mmm_unb1_reorder IS
     reg_diag_data_buf_re_miso : IN  t_mem_miso;
     
     reg_bsn_monitor_mosi      : OUT t_mem_mosi;
-    reg_bsn_monitor_miso      : IN  t_mem_miso
+    reg_bsn_monitor_miso      : IN  t_mem_miso;
+    
+    -- IO DDR register map 
+    reg_io_ddr_mosi           : OUT t_mem_mosi;
+    reg_io_ddr_miso           : IN  t_mem_miso
   );
 END mmm_unb1_reorder;
 
@@ -229,6 +233,9 @@ BEGIN
     u_mm_file_reg_bsn_monitor      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
                                              PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso);
 
+    u_mm_file_reg_io_ddr           : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+                                             PORT MAP(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+
     ----------------------------------------------------------------------------
     -- 1GbE setup sequence normally performed by unb_os@NIOS
     ----------------------------------------------------------------------------

applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd

@@ -64,7 +64,11 @@ PORT (
     out_siso_arr          : IN  t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
     out_sosi_arr          : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
     
-    -- DDR3 transpose       
+    -- IO DDR register map 
+    reg_io_ddr_mosi       : IN  t_mem_mosi;
+    reg_io_ddr_miso       : OUT t_mem_miso;
+    
+    -- Reorder transpose       
     ram_ss_ss_transp_mosi : IN  t_mem_mosi; 
     ram_ss_ss_transp_miso : OUT t_mem_miso; 
 
@@ -188,6 +192,15 @@ BEGIN
     ctlr_clk_in   => dp_clk,  
     ctlr_rst_in   => dp_rst,  
 
+    -- MM clock + reset
+    mm_rst        => mm_rst,
+    mm_clk        => mm_clk,     
+    
+    -- MM register map for DDR controller status info
+    reg_io_ddr_mosi => reg_io_ddr_mosi,
+    reg_io_ddr_miso => reg_io_ddr_miso,
+
+
     -- Driver clock domain
     dvr_clk       => dp_clk,
     dvr_rst       => dp_rst,

applications/unb1_reorder/src/vhdl/unb1_reorder.vhd

@@ -199,9 +199,13 @@ ARCHITECTURE str OF unb1_reorder IS
   SIGNAL eth1g_ram_mosi             : t_mem_mosi := c_mem_mosi_rst;  -- ETH rx frame and tx frame memory
   SIGNAL eth1g_ram_miso             : t_mem_miso;
 
-  -- DDR3 Transpose
+  -- Reorder Transpose
   SIGNAL ram_ss_ss_transp_mosi      : t_mem_mosi;
-  SIGNAL ram_ss_ss_transp_miso      : t_mem_miso;  
+  SIGNAL ram_ss_ss_transp_miso      : t_mem_miso;       
+  
+  -- IO DDR register map 
+  SIGNAL reg_io_ddr_mosi            : t_mem_mosi;       
+  SIGNAL reg_io_ddr_miso            : t_mem_miso;       
   
    -- . UniBoard I2C sens                         
   SIGNAL reg_unb_sens_mosi          : t_mem_mosi;
@@ -423,7 +427,12 @@ BEGIN
 
     -- BSN monitor
     reg_bsn_monitor_mosi      => reg_bsn_monitor_mosi,
-    reg_bsn_monitor_miso      => reg_bsn_monitor_miso
+    reg_bsn_monitor_miso      => reg_bsn_monitor_miso,
+
+    -- IO DDR register map 
+    reg_io_ddr_mosi           => reg_io_ddr_mosi,
+    reg_io_ddr_miso           => reg_io_ddr_miso
+    
   );
   
   u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
@@ -469,7 +478,11 @@ BEGIN
     out_siso_arr          => data_buf_snk_out_siso_arr,
     out_sosi_arr          => data_buf_snk_in_sosi_arr,
     
-    -- DDR3 transpose      
+    -- IO DDR register map 
+    reg_io_ddr_mosi       => reg_io_ddr_mosi,
+    reg_io_ddr_miso       => reg_io_ddr_miso,
+    
+    -- Reorder transpose      
     ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
     ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,