Merge branch 'RTSD-180' into 'master'

Porting fifo for Intel Agilex 7

Closes RTSD-180

See merge request !362

libraries/technology/fifo/hdllib.cfg

 hdl_lib_name = tech_fifo
 hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo ip_agi027_xxxx_fifo
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 hdl_lib_disclose_library_clause_names =
@@ -10,6 +10,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e1sg_fifo   ip_arria10_e1sg_fifo_lib
     ip_arria10_e2sg_fifo   ip_arria10_e2sg_fifo_lib
     ip_ultrascale_fifo     ip_arria10_ultrascale_lib
+    ip_agi027_xxxx_fifo    ip_agi027_xxxx_fifo_lib
 
 synth_files =
     tech_fifo_component_pkg.vhd

libraries/technology/fifo/tech_fifo_component_pkg.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright (C) 2014
+-- Copyright 2014-2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -- -----------------------------------------------------------------------------
-
--- Purpose: IP components declarations for various devices that get wrapped by the tech components
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Purpose: 
+--   IP components declarations for various devices that get wrapped by the tech components
 
 library IEEE, technology_lib;
 use IEEE.std_logic_1164.all;
@@ -413,4 +415,69 @@ package tech_fifo_component_pkg is
   );
   end component;
 
+  -----------------------------------------------------------------------------
+  -- ip_agi027_xxxx
+  -----------------------------------------------------------------------------
+
+  component ip_agi027_xxxx_fifo_sc is
+  generic (
+    g_use_eab   : string := "ON";
+    g_dat_w     : natural := 20;
+    g_nof_words : natural := 1024
+  );
+  port (
+    aclr    : in std_logic;
+    clock   : in std_logic;
+    data    : in std_logic_vector(g_dat_w - 1 downto 0);
+    rdreq   : in std_logic;
+    wrreq   : in std_logic;
+    empty   : out std_logic;
+    full    : out std_logic;
+    q       : out std_logic_vector(g_dat_w - 1 downto 0);
+    usedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+
+  component ip_agi027_xxxx_fifo_dc is
+  generic (
+    g_use_eab   : string := "ON";
+    g_dat_w     : natural := 20;
+    g_nof_words : natural := 1024
+  );
+  port (
+    aclr    : in std_logic  := '0';
+    data    : in std_logic_vector(g_dat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q       : out std_logic_vector(g_dat_w - 1 downto 0);
+    rdempty : out std_logic;
+    rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
+    wrfull  : out std_logic;
+    wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+
+  component ip_agi027_xxxx_fifo_dc_mixed_widths is
+  generic (
+    g_nof_words : natural := 1024;  -- FIFO size in nof wr_dat words
+    g_wrdat_w   : natural := 20;
+    g_rddat_w   : natural := 10
+  );
+  port (
+    aclr    : in std_logic  := '0';
+    data    : in std_logic_vector(g_wrdat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q       : out std_logic_vector(g_rddat_w - 1 downto 0);
+    rdempty : out std_logic;
+    rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+    wrfull  : out std_logic;
+    wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+
 end tech_fifo_component_pkg;

libraries/technology/fifo/tech_fifo_dc.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright (C) 2014
+-- Copyright 2014-2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
 
 library ieee, technology_lib;
 use ieee.std_logic_1164.all;
@@ -32,6 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
 library ip_arria10_e1sg_fifo_lib;
 library ip_arria10_e2sg_fifo_lib;
 library ip_ultrascale_fifo_lib;
+library ip_agi027_xxxx_fifo_lib;
 
 entity tech_fifo_dc is
   generic (
@@ -93,4 +96,10 @@ begin
     port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   end generate;
 
+  gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+    u0 : ip_agi027_xxxx_fifo_dc
+    generic map (g_use_eab, g_dat_w, g_nof_words)
+    port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  end generate;
+
 end architecture;

libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright (C) 2014
+-- Copyright 2014-2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
 
 library ieee, technology_lib;
 use ieee.std_logic_1164.all;
@@ -32,6 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
 library ip_arria10_e1sg_fifo_lib;
 library ip_arria10_e2sg_fifo_lib;
 library ip_ultrascale_fifo_lib;
+library ip_agi027_xxxx_fifo_lib;
 
 entity tech_fifo_dc_mixed_widths is
   generic (
@@ -93,4 +96,10 @@ begin
     port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   end generate;
 
+  gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+    u0 : ip_agi027_xxxx_fifo_dc_mixed_widths
+    generic map (g_nof_words, g_wrdat_w, g_rddat_w)
+    port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  end generate;
+
 end architecture;

libraries/technology/fifo/tech_fifo_sc.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright (C) 2014
+-- Copyright 2014-2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
 
 library ieee, technology_lib;
 use ieee.std_logic_1164.all;
@@ -32,6 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
 library ip_arria10_e1sg_fifo_lib;
 library ip_arria10_e2sg_fifo_lib;
 library ip_ultrascale_fifo_lib;
+library ip_agi027_xxxx_fifo_lib;
 
 entity tech_fifo_sc is
   generic (
@@ -91,4 +94,10 @@ begin
     port map (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
   end generate;
 
+  gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+    u0 : ip_agi027_xxxx_fifo_sc
+    generic map (g_use_eab, g_dat_w, g_nof_words)
+    port map (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+  end generate;
+
 end architecture;

libraries/technology/ip_agi027_xxxx/fifo/README.txt

+README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/fifo
+
+Contents:
+
+1) FIFO components
+2) Agilex7 IP
+3) Implementation options (LUTs or block RAM)
+4) Synthesis trials
+5) Issues
+
+
+1) FIFO components:
+
+  ip_agi027_xxxx_fifo_sc              = Single clock FIFO
+  ip_agi027_xxxx_fifo_dc              = Dual clock FIFO
+  ip_agi027_xxxx_fifo_dc_mixed_widths = Dual clock FIFO with different read and write data widths (ratio power of 2)
+  
+
+2) Agilex7 IP
+
+  The IP was ported from arria10_e2sg by:
+  
+   - methode A:
+    . copy original ip_arria_e2sg_<fifo_name>.vhd and ip_arria_e2sg_<fifo_name>.ip files.
+    . rename ip_arria_e2sg_<fifo_name>.ip and .vhd into ip_agi027_xxxx_<fifo_name>.ip and .vhd (also replace name inside the .vhd file)
+    . open in to Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB. 
+      Finish automatically convert to "new" IP, note differences such as version.
+    . then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build directory using the 
+      terminal command generate_ip_libs <buildset> and finish to save the changes.
+    . compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if 
+      necessary to make it work.
+    . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original if case it needs to be modified.
+
+   - methode B:
+    . copy original ip_arria_e2sg_<fifo_name>.vhd file.
+    . rename ip_arria_e2sg_<fifo_name>.vhd into ip_agi027_xxxx_<fifo_name>.vhd (also replace name inside the .vhd file).
+    . open ip_arria_e2sg_<fifo_name>.ip file in Quartus 19.4.0 build 64. No device family and device part need to be set.
+    . open also Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
+    . select the corresponding IP in the IP catalog in Quartus 23.2.0 and provide the filename as ip_agi027_xxxx_<fifo_name>.ip
+      Finish automatically convert to IP, note differences such as version.
+    . save the changes and then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build 
+      directory using the terminal command generate_ip_libs <buildset> to finish it.
+    . compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if 
+      necessary to make it work.
+    . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original if case it needs to be modified.
+
+
+  this yields:
+  
+    ip_agi027_xxxx_fifo_sc.ip
+    ip_agi027_xxxx_fifo_dc.ip
+    ip_agi027_xxxx_fifo_dc_mixed_widths.ip
+  
+  The Agilex7 FIFO IP still uses the altera_mf package (so not the altera_lnsim package as with the block RAM). The
+  FIFOs map to the altera_mf components to scfifo, dcfifo and dcfifo_mixed_widths.
+  
+  The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_xxxx_fifo_*.vhd
+  directly instantiates the altera_mf component. The buildset for the agi027_xxxx is iwave.
+  
+  The instantiation is copied manually from the ip_agi027_xxxx_fifo_*/fifo_1921/sim/ip_agi027_xxxxg_fifo_*.vhd and 
+  saved in the ip_agi027_xxxx_<fifo_name>.vhd file. So then the generated HDL files are no longer needed, because it could easily be derived 
+  from the IP file and the files will be generated in the build directory (under iwave/qsys-generate/) when using the terminal commando 
+  generate_ip_libs <buildset>. 
+   
+
+3) Implementation options (LUTs or block RAM)
+
+  The IP FIFO can be set to use LUTs (MLAB) or block RAM (M20K and M144K) via g_use_eab.
+  
+
+4) Synthesis trials
+
+  The quartus/fifo.qsf could be derived from the ip_arria10/fifo/ folder and changed to only the following assignments:
+    set_global_assignment -name FAMILY "Agilex 7"
+    set_global_assignment -name DEVICE AGIB027R31A1I1VB
+    set_global_assignment -name LAST_QUARTUS_VERSION "23.2.0 Pro Edition"
+    set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+    set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+    set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+    set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
+    set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
+    set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
+  quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_xxxx/fifo/quartus/fifo.qsf could be added to the hdllib.cfg under
+  [quartus_project_file]. Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
+  The Quartus project ip_agi027_xxxx_fif.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_fifo/ was used to verify that the FIFO IP 
+  actually synthesise to the appropriate FPGA resources. Use the Quartus GUI to manually select a top level component for synthesis e.g. 
+  by right clicking the entity vhd file in the file tab of the Quartus project navigator window. For the (default) testcondition the 
+  generics are set to 1024 words deep and 20 bits wide. Then check the resource usage in the synthesis and fitter reports.
+  The most important information from these reports is (found under Place Stage > Resource Usage Summary / Resource Utilazation by Entity):
+      . for g_nof_words is 1024 and for g_wrdat_w is 20, exactly fills one M20k block ram. 20 * 1024 = 20480 block memory bits.
+      . the total M20K blocks is 13272. Thus the total block memory bits that is available 13272 * 20480 = 271810560 when optimal use.
+      . no dsp blocks are used.
+      . the ALM needed [=A-B+C] for dc_mixed_widths is 119.
+      . the ALM needed [=A-B+C] for dc is 113.
+      . the ALM needed [=A-B+C] for sc is 30.
+      . the total ALMs on device is 912800.
+
+
+5) Issues
+
+  No issues.

libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg

+hdl_lib_name = ip_agi027_xxxx_fifo
+hdl_library_clause_name = ip_agi027_xxxx_fifo_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+    ip_agi027_xxxx_fifo_sc.vhd
+    ip_agi027_xxxx_fifo_dc.vhd
+    ip_agi027_xxxx_fifo_dc_mixed_widths.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity = 
+
+quartus_qsf_files =
+
+
+[generate_ip_libs]
+qsys-generate_ip_files = 

libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose: 
+--   RadioHDL wrapper / Instantiate FIFO IP with generics
+-- Description:
+--   Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_dc_fifo_1921_kss5lzq.vhd
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library altera_mf;
+use altera_mf.all;
+
+entity ip_agi027_xxxx_fifo_dc is
+  generic (
+    g_use_eab   : string := "ON";
+    g_dat_w     : natural := 20;
+    g_nof_words : natural := 1024
+  );
+  port (
+    aclr    : in std_logic  := '0';
+    data    : in std_logic_vector(g_dat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q       : out std_logic_vector(g_dat_w - 1 downto 0);
+    rdempty : out std_logic;
+    rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
+    wrfull  : out std_logic;
+    wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+end ip_agi027_xxxx_fifo_dc;
+
+architecture SYN of ip_agi027_xxxx_fifo_dc is
+    component  dcfifo
+    generic (
+        -- enable_ecc  : string;
+        intended_device_family  : string;
+        -- lpm_hint  : string;
+        lpm_numwords  : natural;
+        lpm_showahead  : string;
+        lpm_type  : string;
+        lpm_width  : natural;
+        lpm_widthu  : natural;
+        overflow_checking  : string;
+        rdsync_delaypipe  : natural;
+        read_aclr_synch  : string;
+        underflow_checking  : string;
+        use_eab  : string;
+        write_aclr_synch  : string;
+        wrsync_delaypipe  : natural
+    );
+    port (
+        aclr   : in std_logic;
+        data   : in std_logic_vector(g_dat_w - 1 downto 0);
+        rdclk   : in std_logic;
+        rdreq   : in std_logic;
+        wrclk   : in std_logic;
+        wrreq   : in std_logic;
+        q   : out std_logic_vector(g_dat_w - 1 downto 0);
+        rdempty   : out std_logic;
+        rdusedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
+        wrfull   : out std_logic;
+        wrusedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+    );
+    end component;
+begin
+  u_dcfifo : dcfifo
+  generic map (
+    -- enable_ecc  => "FALSE",
+    intended_device_family  => "Agilex 7",
+    -- lpm_hint  => "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
+    lpm_numwords  => g_nof_words,
+    lpm_showahead  => "OFF",
+    lpm_type  => "dcfifo",
+    lpm_width  => g_dat_w,
+    lpm_widthu  => tech_ceil_log2(g_nof_words),
+    overflow_checking  => "ON",
+    rdsync_delaypipe  => 5,
+    read_aclr_synch  => "OFF",
+    underflow_checking  => "ON",
+    use_eab  => g_use_eab,
+    write_aclr_synch  => "ON",
+    wrsync_delaypipe  => 5
+  )
+  port map (
+    aclr => aclr,
+    data => data,
+    rdclk => rdclk,
+    rdreq => rdreq,
+    wrclk => wrclk,
+    wrreq => wrreq,
+    q => q,
+    rdempty => rdempty,
+    rdusedw => rdusedw,
+    wrfull => wrfull,
+    wrusedw => wrusedw
+  );
+end SYN;

libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose: 
+--   RadioHDL wrapper / Instantiate FIFO IP with generics
+-- Description:
+--   Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_dc_mixed_widths_fifo_1921_qaaak5a.vhd
+-- Remark:
+--   Default value for g_nof_words is 1024 and for g_wrdat_w is 20, exactly fills one M20k block ram. 20 * 1024 = 20480 block memory bits.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library altera_mf;
+use altera_mf.all;
+
+entity ip_agi027_xxxx_fifo_dc_mixed_widths is
+  generic (
+    g_nof_words : natural := 1024;  -- FIFO size in nof wr_dat words;
+    g_wrdat_w   : natural := 20;
+    g_rddat_w   : natural := 10     
+  );
+  port (
+    aclr    : in std_logic  := '0';
+    data    : in std_logic_vector(g_wrdat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q       : out std_logic_vector(g_rddat_w - 1 downto 0);
+    rdempty : out std_logic;
+    rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+    wrfull  : out std_logic;
+    wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+end ip_agi027_xxxx_fifo_dc_mixed_widths;
+
+architecture SYN of ip_agi027_xxxx_fifo_dc_mixed_widths is
+  component  dcfifo_mixed_widths
+  generic (
+    -- enable_ecc  : string;
+    intended_device_family  : string;
+    -- lpm_hint  : string;
+    lpm_numwords  : natural;
+    lpm_showahead  : string;
+    lpm_type  : string;
+    lpm_width  : natural;
+    lpm_widthu  : natural;
+    lpm_widthu_r  : natural;
+    lpm_width_r  : natural;
+    overflow_checking  : string;
+    rdsync_delaypipe  : natural;
+    read_aclr_synch  : string;
+    underflow_checking  : string;
+    use_eab  : string;
+    write_aclr_synch  : string;
+    wrsync_delaypipe  : natural
+  );
+  port (
+    aclr   : in std_logic;
+    data   : in std_logic_vector(g_wrdat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q   : out std_logic_vector(g_rddat_w - 1 downto 0);
+    rdempty   : out std_logic;
+    rdusedw   : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+    wrfull   : out std_logic;
+    wrusedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+begin
+  dcfifo_mixed_widths_component : dcfifo_mixed_widths
+  generic map (
+    -- enable_ecc  => "FALSE",
+    intended_device_family  => "Agilex 7",
+    -- lpm_hint  => "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
+    lpm_numwords  => g_nof_words,
+    lpm_showahead  => "OFF",
+    lpm_type  => "dcfifo_mixed_widths",
+    lpm_width  => g_wrdat_w,
+    lpm_widthu  => tech_ceil_log2(g_nof_words),
+    lpm_widthu_r  => tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w),
+    lpm_width_r  => g_rddat_w,
+    overflow_checking  => "ON",
+    rdsync_delaypipe  => 5,
+    read_aclr_synch  => "OFF",
+    underflow_checking  => "ON",
+    use_eab  => "ON",
+    write_aclr_synch  => "ON",
+    wrsync_delaypipe  => 5
+  )
+  port map (
+    aclr => aclr,
+    data => data,
+    rdclk => rdclk,
+    rdreq => rdreq,
+    wrclk => wrclk,
+    wrreq => wrreq,
+    q => q,
+    rdempty => rdempty,
+    rdusedw => rdusedw,
+    wrfull => wrfull,
+    wrusedw => wrusedw
+  );
+end SYN;

libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose: 
+--   RadioHDL wrapper / Instantiate FIFO IP with generics
+-- Description:
+--   Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_sc_fifo_1921_7egef6q.vhd
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library altera_mf;
+use altera_mf.all;
+
+entity ip_agi027_xxxx_fifo_sc is
+  generic (
+    g_use_eab   : string := "ON";
+    g_dat_w     : natural := 20;
+    g_nof_words : natural := 1024
+  );
+  port (
+    aclr    : in std_logic;
+    clock   : in std_logic;
+    data    : in std_logic_vector(g_dat_w - 1 downto 0);
+    rdreq   : in std_logic;
+    wrreq   : in std_logic;
+    empty   : out std_logic;
+    full    : out std_logic;
+    q       : out std_logic_vector(g_dat_w - 1 downto 0);
+    usedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+end ip_agi027_xxxx_fifo_sc;
+
+architecture SYN of ip_agi027_xxxx_fifo_sc is
+  component  scfifo
+  generic (
+      add_ram_output_register  : string;
+      -- enable_ecc  : string;
+      intended_device_family  : string;
+      lpm_numwords  : natural;
+      lpm_showahead  : string;
+      lpm_type  : string;
+      lpm_width  : natural;
+      lpm_widthu  : natural;
+      overflow_checking  : string;
+      underflow_checking  : string;
+      use_eab  : string
+  );
+  port (
+      aclr   : in std_logic;
+      clock   : in std_logic;
+      data   : in std_logic_vector(g_dat_w - 1 downto 0);
+      rdreq   : in std_logic;
+      wrreq   : in std_logic;
+      empty   : out std_logic;
+      full   : out std_logic;
+      q   : out std_logic_vector(g_dat_w - 1 downto 0);
+      usedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+begin
+  u_scfifo : scfifo
+  generic map (
+    add_ram_output_register  => "ON",
+    -- enable_ecc  => "FALSE",
+    intended_device_family  => "Agilex 7",
+    lpm_numwords  => g_nof_words,
+    lpm_showahead  => "OFF",
+    lpm_type  => "scfifo",
+    lpm_width  => g_dat_w,
+    lpm_widthu  => tech_ceil_log2(g_nof_words),
+    overflow_checking  => "ON",
+    underflow_checking  => "ON",
+    use_eab  => g_use_eab
+  )
+  port map (
+    aclr => aclr,
+    clock => clock,
+    data => data,
+    rdreq => rdreq,
+    wrreq => wrreq,
+    empty => empty,
+    full => full,
+    q => q,
+    usedw => usedw
+  );
+end SYN;