diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index 292b8492dd0f004cecd8a519e9e270e34223d0ee..2e99c33328224c87312410edb5f0742025885311 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_fifo
hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo ip_agi027_xxxx_fifo
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -10,6 +10,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_fifo ip_arria10_e1sg_fifo_lib
ip_arria10_e2sg_fifo ip_arria10_e2sg_fifo_lib
ip_ultrascale_fifo ip_arria10_ultrascale_lib
+ ip_agi027_xxxx_fifo ip_agi027_xxxx_fifo_lib
synth_files =
tech_fifo_component_pkg.vhd
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index d57f837edd08425727af72d22f2bdb0465058844..ff35a5e738ab328f46bc9b09296bc7e3cf193d0e 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -1,25 +1,27 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
-
--- Purpose: IP components declarations for various devices that get wrapped by the tech components
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Purpose:
+-- IP components declarations for various devices that get wrapped by the tech components
library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
@@ -413,4 +415,69 @@ package tech_fifo_component_pkg is
);
end component;
+ -----------------------------------------------------------------------------
+ -- ip_agi027_xxxx
+ -----------------------------------------------------------------------------
+
+ component ip_agi027_xxxx_fifo_sc is
+ generic (
+ g_use_eab : string := "ON";
+ g_dat_w : natural := 20;
+ g_nof_words : natural := 1024
+ );
+ port (
+ aclr : in std_logic;
+ clock : in std_logic;
+ data : in std_logic_vector(g_dat_w - 1 downto 0);
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
+ usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_fifo_dc is
+ generic (
+ g_use_eab : string := "ON";
+ g_dat_w : natural := 20;
+ g_nof_words : natural := 1024
+ );
+ port (
+ aclr : in std_logic := '0';
+ data : in std_logic_vector(g_dat_w - 1 downto 0);
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
+ rdempty : out std_logic;
+ rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
+ wrfull : out std_logic;
+ wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_fifo_dc_mixed_widths is
+ generic (
+ g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : natural := 20;
+ g_rddat_w : natural := 10
+ );
+ port (
+ aclr : in std_logic := '0';
+ data : in std_logic_vector(g_wrdat_w - 1 downto 0);
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
+ q : out std_logic_vector(g_rddat_w - 1 downto 0);
+ rdempty : out std_logic;
+ rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+ wrfull : out std_logic;
+ wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+ end component;
+
end tech_fifo_component_pkg;
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index c2f8207953d00f34d9bb8b740b9f8fa6d0e65302..750e3f0f344405f75240393fe33031f9a0ed22ed 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -32,6 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
library ip_arria10_e1sg_fifo_lib;
library ip_arria10_e2sg_fifo_lib;
library ip_ultrascale_fifo_lib;
+library ip_agi027_xxxx_fifo_lib;
entity tech_fifo_dc is
generic (
@@ -93,4 +96,10 @@ begin
port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
end generate;
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_fifo_dc
+ generic map (g_use_eab, g_dat_w, g_nof_words)
+ port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ end generate;
+
end architecture;
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index 502fb8bb3928f4cd7d919eb00534df44cfbe993b..9734ed8e27030e1584341a74ea1786d6895f37db 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -32,6 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
library ip_arria10_e1sg_fifo_lib;
library ip_arria10_e2sg_fifo_lib;
library ip_ultrascale_fifo_lib;
+library ip_agi027_xxxx_fifo_lib;
entity tech_fifo_dc_mixed_widths is
generic (
@@ -93,4 +96,10 @@ begin
port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
end generate;
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_fifo_dc_mixed_widths
+ generic map (g_nof_words, g_wrdat_w, g_rddat_w)
+ port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ end generate;
+
end architecture;
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 53f9427bb11f059bb4a9ae6a7cbb8a57c895804b..d6bbdfe7e744de6045a0f6a7c27fdeaee05fa5f2 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -32,6 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
library ip_arria10_e1sg_fifo_lib;
library ip_arria10_e2sg_fifo_lib;
library ip_ultrascale_fifo_lib;
+library ip_agi027_xxxx_fifo_lib;
entity tech_fifo_sc is
generic (
@@ -91,4 +94,10 @@ begin
port map (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
end generate;
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_fifo_sc
+ generic map (g_use_eab, g_dat_w, g_nof_words)
+ port map (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+ end generate;
+
end architecture;
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/README.txt b/libraries/technology/ip_agi027_xxxx/fifo/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e88d724fd4de6ef97cf899387f009ec9c56be7aa
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/fifo/README.txt
@@ -0,0 +1,101 @@
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/fifo
+
+Contents:
+
+1) FIFO components
+2) Agilex7 IP
+3) Implementation options (LUTs or block RAM)
+4) Synthesis trials
+5) Issues
+
+
+1) FIFO components:
+
+ ip_agi027_xxxx_fifo_sc = Single clock FIFO
+ ip_agi027_xxxx_fifo_dc = Dual clock FIFO
+ ip_agi027_xxxx_fifo_dc_mixed_widths = Dual clock FIFO with different read and write data widths (ratio power of 2)
+
+
+2) Agilex7 IP
+
+ The IP was ported from arria10_e2sg by:
+
+ - methode A:
+ . copy original ip_arria_e2sg_<fifo_name>.vhd and ip_arria_e2sg_<fifo_name>.ip files.
+ . rename ip_arria_e2sg_<fifo_name>.ip and .vhd into ip_agi027_xxxx_<fifo_name>.ip and .vhd (also replace name inside the .vhd file)
+ . open in to Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
+ Finish automatically convert to "new" IP, note differences such as version.
+ . then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build directory using the
+ terminal command generate_ip_libs <buildset> and finish to save the changes.
+ . compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
+ necessary to make it work.
+ . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original if case it needs to be modified.
+
+ - methode B:
+ . copy original ip_arria_e2sg_<fifo_name>.vhd file.
+ . rename ip_arria_e2sg_<fifo_name>.vhd into ip_agi027_xxxx_<fifo_name>.vhd (also replace name inside the .vhd file).
+ . open ip_arria_e2sg_<fifo_name>.ip file in Quartus 19.4.0 build 64. No device family and device part need to be set.
+ . open also Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
+ . select the corresponding IP in the IP catalog in Quartus 23.2.0 and provide the filename as ip_agi027_xxxx_<fifo_name>.ip
+ Finish automatically convert to IP, note differences such as version.
+ . save the changes and then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build
+ directory using the terminal command generate_ip_libs <buildset> to finish it.
+ . compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
+ necessary to make it work.
+ . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original if case it needs to be modified.
+
+
+ this yields:
+
+ ip_agi027_xxxx_fifo_sc.ip
+ ip_agi027_xxxx_fifo_dc.ip
+ ip_agi027_xxxx_fifo_dc_mixed_widths.ip
+
+ The Agilex7 FIFO IP still uses the altera_mf package (so not the altera_lnsim package as with the block RAM). The
+ FIFOs map to the altera_mf components to scfifo, dcfifo and dcfifo_mixed_widths.
+
+ The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_xxxx_fifo_*.vhd
+ directly instantiates the altera_mf component. The buildset for the agi027_xxxx is iwave.
+
+ The instantiation is copied manually from the ip_agi027_xxxx_fifo_*/fifo_1921/sim/ip_agi027_xxxxg_fifo_*.vhd and
+ saved in the ip_agi027_xxxx_<fifo_name>.vhd file. So then the generated HDL files are no longer needed, because it could easily be derived
+ from the IP file and the files will be generated in the build directory (under iwave/qsys-generate/) when using the terminal commando
+ generate_ip_libs <buildset>.
+
+
+3) Implementation options (LUTs or block RAM)
+
+ The IP FIFO can be set to use LUTs (MLAB) or block RAM (M20K and M144K) via g_use_eab.
+
+
+4) Synthesis trials
+
+ The quartus/fifo.qsf could be derived from the ip_arria10/fifo/ folder and changed to only the following assignments:
+ set_global_assignment -name FAMILY "Agilex 7"
+ set_global_assignment -name DEVICE AGIB027R31A1I1VB
+ set_global_assignment -name LAST_QUARTUS_VERSION "23.2.0 Pro Edition"
+ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+ set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+ set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
+ set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
+ set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
+ quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_xxxx/fifo/quartus/fifo.qsf could be added to the hdllib.cfg under
+ [quartus_project_file]. Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
+ The Quartus project ip_agi027_xxxx_fif.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_fifo/ was used to verify that the FIFO IP
+ actually synthesise to the appropriate FPGA resources. Use the Quartus GUI to manually select a top level component for synthesis e.g.
+ by right clicking the entity vhd file in the file tab of the Quartus project navigator window. For the (default) testcondition the
+ generics are set to 1024 words deep and 20 bits wide. Then check the resource usage in the synthesis and fitter reports.
+ The most important information from these reports is (found under Place Stage > Resource Usage Summary / Resource Utilazation by Entity):
+ . for g_nof_words is 1024 and for g_wrdat_w is 20, exactly fills one M20k block ram. 20 * 1024 = 20480 block memory bits.
+ . the total M20K blocks is 13272. Thus the total block memory bits that is available 13272 * 20480 = 271810560 when optimal use.
+ . no dsp blocks are used.
+ . the ALM needed [=A-B+C] for dc_mixed_widths is 119.
+ . the ALM needed [=A-B+C] for dc is 113.
+ . the ALM needed [=A-B+C] for sc is 30.
+ . the total ALMs on device is 912800.
+
+
+5) Issues
+
+ No issues.
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..8aa3ed16ba41dd954361ff993ed50c5dd3dfd244
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_agi027_xxxx_fifo
+hdl_library_clause_name = ip_agi027_xxxx_fifo_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+ ip_agi027_xxxx_fifo_sc.vhd
+ ip_agi027_xxxx_fifo_dc.vhd
+ ip_agi027_xxxx_fifo_dc_mixed_widths.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_qsf_files =
+
+
+[generate_ip_libs]
+qsys-generate_ip_files =
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.ip b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.ip
new file mode 100644
index 0000000000000000000000000000000000000000..712f62c90292bff9986aae068689cfaeea5b7221
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.ip
@@ -0,0 +1,657 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_fifo_dc</ipxact:library>
+ <ipxact:name>fifo_0</ipxact:name>
+ <ipxact:version>19.2.1</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>fifo_input</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datain</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>data</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wrreq</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrreq</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdreq</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdreq</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wrclk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrclk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdclk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdclk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>fifo_output</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataout</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>q</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdusedw</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdusedw</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wrusedw</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrusedw</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdempty</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdempty</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wrfull</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrfull</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>fifo</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>data</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrreq</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdreq</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrclk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdclk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>q</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdusedw</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrusedw</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdempty</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrfull</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_fifo_dc</ipxact:library>
+ <ipxact:name>fifo</ipxact:name>
+ <ipxact:version>19.2.1</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device Family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Clock" type="int">
+ <ipxact:name>GUI_Clock</ipxact:name>
+ <ipxact:displayName>Do you want a common clock for reading and writing the FIFO?</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLOCKS_ARE_SYNCHRONIZED" type="int">
+ <ipxact:name>GUI_CLOCKS_ARE_SYNCHRONIZED</ipxact:name>
+ <ipxact:displayName>Are the FIFO clocks synchronized?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_delaypipe" type="int">
+ <ipxact:name>GUI_delaypipe</ipxact:name>
+ <ipxact:displayName>Which type of optimization do you want?</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_synStage" type="int">
+ <ipxact:name>GUI_synStage</ipxact:name>
+ <ipxact:displayName>How many sync stages?</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LegacyRREQ" type="int">
+ <ipxact:name>GUI_LegacyRREQ</ipxact:name>
+ <ipxact:displayName>Which kind of read access do you want with the 'rdreq' signal?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RAM_BLOCK_TYPE" type="string">
+ <ipxact:name>GUI_RAM_BLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>What should the memory block type be?</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Optimize" type="int">
+ <ipxact:name>GUI_Optimize</ipxact:name>
+ <ipxact:displayName>Would you like to register the output to maximize performance but use more area?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Optimize_max" type="int">
+ <ipxact:name>GUI_Optimize_max</ipxact:name>
+ <ipxact:displayName>Which type of optimization do you want?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Width" type="int">
+ <ipxact:name>GUI_Width</ipxact:name>
+ <ipxact:displayName>How wide should the FIFO be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Depth" type="int">
+ <ipxact:name>GUI_Depth</ipxact:name>
+ <ipxact:displayName>How deep should the FIFO be?</ipxact:displayName>
+ <ipxact:value>256</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_output_width" type="int">
+ <ipxact:name>GUI_output_width</ipxact:name>
+ <ipxact:displayName></ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostFullThr" type="int">
+ <ipxact:name>GUI_AlmostFullThr</ipxact:name>
+ <ipxact:displayName>becomes true when usedw[] is greater than or equal to</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostEmptyThr" type="int">
+ <ipxact:name>GUI_AlmostEmptyThr</ipxact:name>
+ <ipxact:displayName>becomes true when usedw[] is less than</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH" type="string">
+ <ipxact:name>GUI_MAX_DEPTH</ipxact:name>
+ <ipxact:displayName>Set the maximum block depth to</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" type="bit">
+ <ipxact:name>GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT</ipxact:name>
+ <ipxact:displayName>Generate SDC file and disable embedded timing constraint</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_diff_widths" type="bit">
+ <ipxact:name>GUI_diff_widths</ipxact:name>
+ <ipxact:displayName>Use a different output width and set to</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Full" type="bit">
+ <ipxact:name>GUI_Full</ipxact:name>
+ <ipxact:displayName>full</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Empty" type="bit">
+ <ipxact:name>GUI_Empty</ipxact:name>
+ <ipxact:displayName>empty</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_UsedW" type="bit">
+ <ipxact:name>GUI_UsedW</ipxact:name>
+ <ipxact:displayName>usedw[] (number of words in the FIFO)</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostFull" type="bit">
+ <ipxact:name>GUI_AlmostFull</ipxact:name>
+ <ipxact:displayName>almost full</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostEmpty" type="bit">
+ <ipxact:name>GUI_AlmostEmpty</ipxact:name>
+ <ipxact:displayName>almost empty</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_sc_aclr" type="bit">
+ <ipxact:name>GUI_sc_aclr</ipxact:name>
+ <ipxact:displayName>Asynchronous clear</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_sc_sclr" type="bit">
+ <ipxact:name>GUI_sc_sclr</ipxact:name>
+ <ipxact:displayName>Synchronous clear (flush the FIFO)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_rsFull" type="bit">
+ <ipxact:name>GUI_rsFull</ipxact:name>
+ <ipxact:displayName>full</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_rsEmpty" type="bit">
+ <ipxact:name>GUI_rsEmpty</ipxact:name>
+ <ipxact:displayName>empty</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_rsUsedW" type="bit">
+ <ipxact:name>GUI_rsUsedW</ipxact:name>
+ <ipxact:displayName>usedw[]</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_wsFull" type="bit">
+ <ipxact:name>GUI_wsFull</ipxact:name>
+ <ipxact:displayName>full</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_wsEmpty" type="bit">
+ <ipxact:name>GUI_wsEmpty</ipxact:name>
+ <ipxact:displayName>empty</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_wsUsedW" type="bit">
+ <ipxact:name>GUI_wsUsedW</ipxact:name>
+ <ipxact:displayName>usedw[]</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_msb_usedw" type="bit">
+ <ipxact:name>GUI_msb_usedw</ipxact:name>
+ <ipxact:displayName>Add an extra MSB to usedw port(s)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_dc_aclr" type="bit">
+ <ipxact:name>GUI_dc_aclr</ipxact:name>
+ <ipxact:displayName>Asynchronous clear</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_write_aclr_synch" type="bit">
+ <ipxact:name>GUI_write_aclr_synch</ipxact:name>
+ <ipxact:displayName>Add circuit to synchronize 'aclr' input with 'wrclk'</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_read_aclr_synch" type="bit">
+ <ipxact:name>GUI_read_aclr_synch</ipxact:name>
+ <ipxact:displayName>Add circuit to synchronize 'aclr' input with 'rdclk'</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_OVERFLOW_CHECKING" type="bit">
+ <ipxact:name>GUI_OVERFLOW_CHECKING</ipxact:name>
+ <ipxact:displayName>Disable overflow checking. Writing to a full FIFO will corrupt contents.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_UNDERFLOW_CHECKING" type="bit">
+ <ipxact:name>GUI_UNDERFLOW_CHECKING</ipxact:name>
+ <ipxact:displayName>Disable underflow checking. Reading from an empty FIFO will corrupt contents.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LE_BasedFIFO" type="bit">
+ <ipxact:name>GUI_LE_BasedFIFO</ipxact:name>
+ <ipxact:displayName>Implement FIFO storage with logic cells only, even if the device contains memory blocks.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH_BY_9" type="bit">
+ <ipxact:name>GUI_MAX_DEPTH_BY_9</ipxact:name>
+ <ipxact:displayName>Reduce RAM usage (decreases speed and increases number of Les). Available if data width is divisible by 9.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ENABLE_ECC" type="bit">
+ <ipxact:name>GUI_ENABLE_ECC</ipxact:name>
+ <ipxact:displayName>Enable error checking and correcting (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TESTBENCH" type="bit">
+ <ipxact:name>GUI_TESTBENCH</ipxact:name>
+ <ipxact:displayName>TESTBENCH</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element fifo_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="fifo_input" altera:internal="fifo_0.fifo_input" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
+ <altera:port_mapping altera:name="data" altera:internal="data"></altera:port_mapping>
+ <altera:port_mapping altera:name="rdclk" altera:internal="rdclk"></altera:port_mapping>
+ <altera:port_mapping altera:name="rdreq" altera:internal="rdreq"></altera:port_mapping>
+ <altera:port_mapping altera:name="wrclk" altera:internal="wrclk"></altera:port_mapping>
+ <altera:port_mapping altera:name="wrreq" altera:internal="wrreq"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="fifo_output" altera:internal="fifo_0.fifo_output" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="q" altera:internal="q"></altera:port_mapping>
+ <altera:port_mapping altera:name="rdempty" altera:internal="rdempty"></altera:port_mapping>
+ <altera:port_mapping altera:name="rdusedw" altera:internal="rdusedw"></altera:port_mapping>
+ <altera:port_mapping altera:name="wrfull" altera:internal="wrfull"></altera:port_mapping>
+ <altera:port_mapping altera:name="wrusedw" altera:internal="wrusedw"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.vhd b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..53097c580a2c01a3646c1cf758637ae7744e2564
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.vhd
@@ -0,0 +1,122 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper / Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_dc_fifo_1921_kss5lzq.vhd
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library altera_mf;
+use altera_mf.all;
+
+entity ip_agi027_xxxx_fifo_dc is
+ generic (
+ g_use_eab : string := "ON";
+ g_dat_w : natural := 20;
+ g_nof_words : natural := 1024
+ );
+ port (
+ aclr : in std_logic := '0';
+ data : in std_logic_vector(g_dat_w - 1 downto 0);
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
+ rdempty : out std_logic;
+ rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
+ wrfull : out std_logic;
+ wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+end ip_agi027_xxxx_fifo_dc;
+
+architecture SYN of ip_agi027_xxxx_fifo_dc is
+ component dcfifo
+ generic (
+ -- enable_ecc : string;
+ intended_device_family : string;
+ -- lpm_hint : string;
+ lpm_numwords : natural;
+ lpm_showahead : string;
+ lpm_type : string;
+ lpm_width : natural;
+ lpm_widthu : natural;
+ overflow_checking : string;
+ rdsync_delaypipe : natural;
+ read_aclr_synch : string;
+ underflow_checking : string;
+ use_eab : string;
+ write_aclr_synch : string;
+ wrsync_delaypipe : natural
+ );
+ port (
+ aclr : in std_logic;
+ data : in std_logic_vector(g_dat_w - 1 downto 0);
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
+ rdempty : out std_logic;
+ rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
+ wrfull : out std_logic;
+ wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+ end component;
+begin
+ u_dcfifo : dcfifo
+ generic map (
+ -- enable_ecc => "FALSE",
+ intended_device_family => "Agilex 7",
+ -- lpm_hint => "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ read_aclr_synch => "OFF",
+ underflow_checking => "ON",
+ use_eab => g_use_eab,
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ port map (
+ aclr => aclr,
+ data => data,
+ rdclk => rdclk,
+ rdreq => rdreq,
+ wrclk => wrclk,
+ wrreq => wrreq,
+ q => q,
+ rdempty => rdempty,
+ rdusedw => rdusedw,
+ wrfull => wrfull,
+ wrusedw => wrusedw
+ );
+end SYN;
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.ip b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.ip
new file mode 100644
index 0000000000000000000000000000000000000000..24b3df372cc96a5aba5fc7f80daf7e6391b75ad7
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.ip
@@ -0,0 +1,657 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_fifo_dc_mixed_widths</ipxact:library>
+ <ipxact:name>fifo_0</ipxact:name>
+ <ipxact:version>19.2.1</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>fifo_input</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datain</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>data</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wrreq</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrreq</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdreq</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdreq</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wrclk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrclk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdclk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdclk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>fifo_output</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataout</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>q</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdusedw</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdusedw</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wrusedw</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrusedw</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdempty</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdempty</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wrfull</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrfull</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>fifo</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>data</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrreq</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdreq</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrclk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdclk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>q</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>15</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdusedw</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>6</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrusedw</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdempty</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrfull</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_fifo_dc_mixed_widths</ipxact:library>
+ <ipxact:name>fifo</ipxact:name>
+ <ipxact:version>19.2.1</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device Family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Clock" type="int">
+ <ipxact:name>GUI_Clock</ipxact:name>
+ <ipxact:displayName>Do you want a common clock for reading and writing the FIFO?</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLOCKS_ARE_SYNCHRONIZED" type="int">
+ <ipxact:name>GUI_CLOCKS_ARE_SYNCHRONIZED</ipxact:name>
+ <ipxact:displayName>Are the FIFO clocks synchronized?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_delaypipe" type="int">
+ <ipxact:name>GUI_delaypipe</ipxact:name>
+ <ipxact:displayName>Which type of optimization do you want?</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_synStage" type="int">
+ <ipxact:name>GUI_synStage</ipxact:name>
+ <ipxact:displayName>How many sync stages?</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LegacyRREQ" type="int">
+ <ipxact:name>GUI_LegacyRREQ</ipxact:name>
+ <ipxact:displayName>Which kind of read access do you want with the 'rdreq' signal?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RAM_BLOCK_TYPE" type="string">
+ <ipxact:name>GUI_RAM_BLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>What should the memory block type be?</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Optimize" type="int">
+ <ipxact:name>GUI_Optimize</ipxact:name>
+ <ipxact:displayName>Would you like to register the output to maximize performance but use more area?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Optimize_max" type="int">
+ <ipxact:name>GUI_Optimize_max</ipxact:name>
+ <ipxact:displayName>Which type of optimization do you want?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Width" type="int">
+ <ipxact:name>GUI_Width</ipxact:name>
+ <ipxact:displayName>How wide should the FIFO be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Depth" type="int">
+ <ipxact:name>GUI_Depth</ipxact:name>
+ <ipxact:displayName>How deep should the FIFO be?</ipxact:displayName>
+ <ipxact:value>256</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_output_width" type="int">
+ <ipxact:name>GUI_output_width</ipxact:name>
+ <ipxact:displayName></ipxact:displayName>
+ <ipxact:value>16</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostFullThr" type="int">
+ <ipxact:name>GUI_AlmostFullThr</ipxact:name>
+ <ipxact:displayName>becomes true when usedw[] is greater than or equal to</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostEmptyThr" type="int">
+ <ipxact:name>GUI_AlmostEmptyThr</ipxact:name>
+ <ipxact:displayName>becomes true when usedw[] is less than</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH" type="string">
+ <ipxact:name>GUI_MAX_DEPTH</ipxact:name>
+ <ipxact:displayName>Set the maximum block depth to</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" type="bit">
+ <ipxact:name>GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT</ipxact:name>
+ <ipxact:displayName>Generate SDC file and disable embedded timing constraint</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_diff_widths" type="bit">
+ <ipxact:name>GUI_diff_widths</ipxact:name>
+ <ipxact:displayName>Use a different output width and set to</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Full" type="bit">
+ <ipxact:name>GUI_Full</ipxact:name>
+ <ipxact:displayName>full</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Empty" type="bit">
+ <ipxact:name>GUI_Empty</ipxact:name>
+ <ipxact:displayName>empty</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_UsedW" type="bit">
+ <ipxact:name>GUI_UsedW</ipxact:name>
+ <ipxact:displayName>usedw[] (number of words in the FIFO)</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostFull" type="bit">
+ <ipxact:name>GUI_AlmostFull</ipxact:name>
+ <ipxact:displayName>almost full</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostEmpty" type="bit">
+ <ipxact:name>GUI_AlmostEmpty</ipxact:name>
+ <ipxact:displayName>almost empty</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_sc_aclr" type="bit">
+ <ipxact:name>GUI_sc_aclr</ipxact:name>
+ <ipxact:displayName>Asynchronous clear</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_sc_sclr" type="bit">
+ <ipxact:name>GUI_sc_sclr</ipxact:name>
+ <ipxact:displayName>Synchronous clear (flush the FIFO)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_rsFull" type="bit">
+ <ipxact:name>GUI_rsFull</ipxact:name>
+ <ipxact:displayName>full</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_rsEmpty" type="bit">
+ <ipxact:name>GUI_rsEmpty</ipxact:name>
+ <ipxact:displayName>empty</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_rsUsedW" type="bit">
+ <ipxact:name>GUI_rsUsedW</ipxact:name>
+ <ipxact:displayName>usedw[]</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_wsFull" type="bit">
+ <ipxact:name>GUI_wsFull</ipxact:name>
+ <ipxact:displayName>full</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_wsEmpty" type="bit">
+ <ipxact:name>GUI_wsEmpty</ipxact:name>
+ <ipxact:displayName>empty</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_wsUsedW" type="bit">
+ <ipxact:name>GUI_wsUsedW</ipxact:name>
+ <ipxact:displayName>usedw[]</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_msb_usedw" type="bit">
+ <ipxact:name>GUI_msb_usedw</ipxact:name>
+ <ipxact:displayName>Add an extra MSB to usedw port(s)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_dc_aclr" type="bit">
+ <ipxact:name>GUI_dc_aclr</ipxact:name>
+ <ipxact:displayName>Asynchronous clear</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_write_aclr_synch" type="bit">
+ <ipxact:name>GUI_write_aclr_synch</ipxact:name>
+ <ipxact:displayName>Add circuit to synchronize 'aclr' input with 'wrclk'</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_read_aclr_synch" type="bit">
+ <ipxact:name>GUI_read_aclr_synch</ipxact:name>
+ <ipxact:displayName>Add circuit to synchronize 'aclr' input with 'rdclk'</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_OVERFLOW_CHECKING" type="bit">
+ <ipxact:name>GUI_OVERFLOW_CHECKING</ipxact:name>
+ <ipxact:displayName>Disable overflow checking. Writing to a full FIFO will corrupt contents.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_UNDERFLOW_CHECKING" type="bit">
+ <ipxact:name>GUI_UNDERFLOW_CHECKING</ipxact:name>
+ <ipxact:displayName>Disable underflow checking. Reading from an empty FIFO will corrupt contents.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LE_BasedFIFO" type="bit">
+ <ipxact:name>GUI_LE_BasedFIFO</ipxact:name>
+ <ipxact:displayName>Implement FIFO storage with logic cells only, even if the device contains memory blocks.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH_BY_9" type="bit">
+ <ipxact:name>GUI_MAX_DEPTH_BY_9</ipxact:name>
+ <ipxact:displayName>Reduce RAM usage (decreases speed and increases number of Les). Available if data width is divisible by 9.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ENABLE_ECC" type="bit">
+ <ipxact:name>GUI_ENABLE_ECC</ipxact:name>
+ <ipxact:displayName>Enable error checking and correcting (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TESTBENCH" type="bit">
+ <ipxact:name>GUI_TESTBENCH</ipxact:name>
+ <ipxact:displayName>TESTBENCH</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element fifo_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="fifo_input" altera:internal="fifo_0.fifo_input" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
+ <altera:port_mapping altera:name="data" altera:internal="data"></altera:port_mapping>
+ <altera:port_mapping altera:name="rdclk" altera:internal="rdclk"></altera:port_mapping>
+ <altera:port_mapping altera:name="rdreq" altera:internal="rdreq"></altera:port_mapping>
+ <altera:port_mapping altera:name="wrclk" altera:internal="wrclk"></altera:port_mapping>
+ <altera:port_mapping altera:name="wrreq" altera:internal="wrreq"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="fifo_output" altera:internal="fifo_0.fifo_output" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="q" altera:internal="q"></altera:port_mapping>
+ <altera:port_mapping altera:name="rdempty" altera:internal="rdempty"></altera:port_mapping>
+ <altera:port_mapping altera:name="rdusedw" altera:internal="rdusedw"></altera:port_mapping>
+ <altera:port_mapping altera:name="wrfull" altera:internal="wrfull"></altera:port_mapping>
+ <altera:port_mapping altera:name="wrusedw" altera:internal="wrusedw"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dd34b1351de9dd1422c1c509952d555e06584fc1
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.vhd
@@ -0,0 +1,128 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper / Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_dc_mixed_widths_fifo_1921_qaaak5a.vhd
+-- Remark:
+-- Default value for g_nof_words is 1024 and for g_wrdat_w is 20, exactly fills one M20k block ram. 20 * 1024 = 20480 block memory bits.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library altera_mf;
+use altera_mf.all;
+
+entity ip_agi027_xxxx_fifo_dc_mixed_widths is
+ generic (
+ g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words;
+ g_wrdat_w : natural := 20;
+ g_rddat_w : natural := 10
+ );
+ port (
+ aclr : in std_logic := '0';
+ data : in std_logic_vector(g_wrdat_w - 1 downto 0);
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
+ q : out std_logic_vector(g_rddat_w - 1 downto 0);
+ rdempty : out std_logic;
+ rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+ wrfull : out std_logic;
+ wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+end ip_agi027_xxxx_fifo_dc_mixed_widths;
+
+architecture SYN of ip_agi027_xxxx_fifo_dc_mixed_widths is
+ component dcfifo_mixed_widths
+ generic (
+ -- enable_ecc : string;
+ intended_device_family : string;
+ -- lpm_hint : string;
+ lpm_numwords : natural;
+ lpm_showahead : string;
+ lpm_type : string;
+ lpm_width : natural;
+ lpm_widthu : natural;
+ lpm_widthu_r : natural;
+ lpm_width_r : natural;
+ overflow_checking : string;
+ rdsync_delaypipe : natural;
+ read_aclr_synch : string;
+ underflow_checking : string;
+ use_eab : string;
+ write_aclr_synch : string;
+ wrsync_delaypipe : natural
+ );
+ port (
+ aclr : in std_logic;
+ data : in std_logic_vector(g_wrdat_w - 1 downto 0);
+ rdclk : in std_logic;
+ rdreq : in std_logic;
+ wrclk : in std_logic;
+ wrreq : in std_logic;
+ q : out std_logic_vector(g_rddat_w - 1 downto 0);
+ rdempty : out std_logic;
+ rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+ wrfull : out std_logic;
+ wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+ end component;
+begin
+ dcfifo_mixed_widths_component : dcfifo_mixed_widths
+ generic map (
+ -- enable_ecc => "FALSE",
+ intended_device_family => "Agilex 7",
+ -- lpm_hint => "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo_mixed_widths",
+ lpm_width => g_wrdat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ lpm_widthu_r => tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w),
+ lpm_width_r => g_rddat_w,
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ read_aclr_synch => "OFF",
+ underflow_checking => "ON",
+ use_eab => "ON",
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ port map (
+ aclr => aclr,
+ data => data,
+ rdclk => rdclk,
+ rdreq => rdreq,
+ wrclk => wrclk,
+ wrreq => wrreq,
+ q => q,
+ rdempty => rdempty,
+ rdusedw => rdusedw,
+ wrfull => wrfull,
+ wrusedw => wrusedw
+ );
+end SYN;
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.ip b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.ip
new file mode 100644
index 0000000000000000000000000000000000000000..6a965da80d13cebf89e02fc1fd955a678ffa3d1e
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.ip
@@ -0,0 +1,609 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_fifo_sc</ipxact:library>
+ <ipxact:name>fifo_0</ipxact:name>
+ <ipxact:version>19.2.1</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>fifo_input</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datain</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>data</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>wrreq</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>wrreq</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>rdreq</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>rdreq</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>fifo_output</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataout</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>q</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>usedw</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>usedw</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>full</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>full</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>empty</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>empty</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>fifo</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>data</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>wrreq</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>rdreq</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>q</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>usedw</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>full</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>empty</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_fifo_sc</ipxact:library>
+ <ipxact:name>fifo</ipxact:name>
+ <ipxact:version>19.2.1</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device Family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Clock" type="int">
+ <ipxact:name>GUI_Clock</ipxact:name>
+ <ipxact:displayName>Do you want a common clock for reading and writing the FIFO?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLOCKS_ARE_SYNCHRONIZED" type="int">
+ <ipxact:name>GUI_CLOCKS_ARE_SYNCHRONIZED</ipxact:name>
+ <ipxact:displayName>Are the FIFO clocks synchronized?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_delaypipe" type="int">
+ <ipxact:name>GUI_delaypipe</ipxact:name>
+ <ipxact:displayName>Which type of optimization do you want?</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_synStage" type="int">
+ <ipxact:name>GUI_synStage</ipxact:name>
+ <ipxact:displayName>How many sync stages?</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LegacyRREQ" type="int">
+ <ipxact:name>GUI_LegacyRREQ</ipxact:name>
+ <ipxact:displayName>Which kind of read access do you want with the 'rdreq' signal?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_RAM_BLOCK_TYPE" type="string">
+ <ipxact:name>GUI_RAM_BLOCK_TYPE</ipxact:name>
+ <ipxact:displayName>What should the memory block type be?</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Optimize" type="int">
+ <ipxact:name>GUI_Optimize</ipxact:name>
+ <ipxact:displayName>Would you like to register the output to maximize performance but use more area?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Optimize_max" type="int">
+ <ipxact:name>GUI_Optimize_max</ipxact:name>
+ <ipxact:displayName>Which type of optimization do you want?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Width" type="int">
+ <ipxact:name>GUI_Width</ipxact:name>
+ <ipxact:displayName>How wide should the FIFO be?</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Depth" type="int">
+ <ipxact:name>GUI_Depth</ipxact:name>
+ <ipxact:displayName>How deep should the FIFO be?</ipxact:displayName>
+ <ipxact:value>256</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_output_width" type="int">
+ <ipxact:name>GUI_output_width</ipxact:name>
+ <ipxact:displayName></ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostFullThr" type="int">
+ <ipxact:name>GUI_AlmostFullThr</ipxact:name>
+ <ipxact:displayName>becomes true when usedw[] is greater than or equal to</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostEmptyThr" type="int">
+ <ipxact:name>GUI_AlmostEmptyThr</ipxact:name>
+ <ipxact:displayName>becomes true when usedw[] is less than</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH" type="string">
+ <ipxact:name>GUI_MAX_DEPTH</ipxact:name>
+ <ipxact:displayName>Set the maximum block depth to</ipxact:displayName>
+ <ipxact:value>Auto</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" type="bit">
+ <ipxact:name>GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT</ipxact:name>
+ <ipxact:displayName>Generate SDC file and disable embedded timing constraint</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_diff_widths" type="bit">
+ <ipxact:name>GUI_diff_widths</ipxact:name>
+ <ipxact:displayName>Use a different output width and set to</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Full" type="bit">
+ <ipxact:name>GUI_Full</ipxact:name>
+ <ipxact:displayName>full</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_Empty" type="bit">
+ <ipxact:name>GUI_Empty</ipxact:name>
+ <ipxact:displayName>empty</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_UsedW" type="bit">
+ <ipxact:name>GUI_UsedW</ipxact:name>
+ <ipxact:displayName>usedw[] (number of words in the FIFO)</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostFull" type="bit">
+ <ipxact:name>GUI_AlmostFull</ipxact:name>
+ <ipxact:displayName>almost full</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AlmostEmpty" type="bit">
+ <ipxact:name>GUI_AlmostEmpty</ipxact:name>
+ <ipxact:displayName>almost empty</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_sc_aclr" type="bit">
+ <ipxact:name>GUI_sc_aclr</ipxact:name>
+ <ipxact:displayName>Asynchronous clear</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_sc_sclr" type="bit">
+ <ipxact:name>GUI_sc_sclr</ipxact:name>
+ <ipxact:displayName>Synchronous clear (flush the FIFO)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_rsFull" type="bit">
+ <ipxact:name>GUI_rsFull</ipxact:name>
+ <ipxact:displayName>full</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_rsEmpty" type="bit">
+ <ipxact:name>GUI_rsEmpty</ipxact:name>
+ <ipxact:displayName>empty</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_rsUsedW" type="bit">
+ <ipxact:name>GUI_rsUsedW</ipxact:name>
+ <ipxact:displayName>usedw[]</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_wsFull" type="bit">
+ <ipxact:name>GUI_wsFull</ipxact:name>
+ <ipxact:displayName>full</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_wsEmpty" type="bit">
+ <ipxact:name>GUI_wsEmpty</ipxact:name>
+ <ipxact:displayName>empty</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_wsUsedW" type="bit">
+ <ipxact:name>GUI_wsUsedW</ipxact:name>
+ <ipxact:displayName>usedw[]</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_msb_usedw" type="bit">
+ <ipxact:name>GUI_msb_usedw</ipxact:name>
+ <ipxact:displayName>Add an extra MSB to usedw port(s)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_dc_aclr" type="bit">
+ <ipxact:name>GUI_dc_aclr</ipxact:name>
+ <ipxact:displayName>Asynchronous clear</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_write_aclr_synch" type="bit">
+ <ipxact:name>GUI_write_aclr_synch</ipxact:name>
+ <ipxact:displayName>Add circuit to synchronize 'aclr' input with 'wrclk'</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_read_aclr_synch" type="bit">
+ <ipxact:name>GUI_read_aclr_synch</ipxact:name>
+ <ipxact:displayName>Add circuit to synchronize 'aclr' input with 'rdclk'</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_OVERFLOW_CHECKING" type="bit">
+ <ipxact:name>GUI_OVERFLOW_CHECKING</ipxact:name>
+ <ipxact:displayName>Disable overflow checking. Writing to a full FIFO will corrupt contents.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_UNDERFLOW_CHECKING" type="bit">
+ <ipxact:name>GUI_UNDERFLOW_CHECKING</ipxact:name>
+ <ipxact:displayName>Disable underflow checking. Reading from an empty FIFO will corrupt contents.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LE_BasedFIFO" type="bit">
+ <ipxact:name>GUI_LE_BasedFIFO</ipxact:name>
+ <ipxact:displayName>Implement FIFO storage with logic cells only, even if the device contains memory blocks.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_MAX_DEPTH_BY_9" type="bit">
+ <ipxact:name>GUI_MAX_DEPTH_BY_9</ipxact:name>
+ <ipxact:displayName>Reduce RAM usage (decreases speed and increases number of Les). Available if data width is divisible by 9.</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_ENABLE_ECC" type="bit">
+ <ipxact:name>GUI_ENABLE_ECC</ipxact:name>
+ <ipxact:displayName>Enable error checking and correcting (ECC)</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_TESTBENCH" type="bit">
+ <ipxact:name>GUI_TESTBENCH</ipxact:name>
+ <ipxact:displayName>TESTBENCH</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element fifo_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="fifo_input" altera:internal="fifo_0.fifo_input" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ <altera:port_mapping altera:name="data" altera:internal="data"></altera:port_mapping>
+ <altera:port_mapping altera:name="rdreq" altera:internal="rdreq"></altera:port_mapping>
+ <altera:port_mapping altera:name="wrreq" altera:internal="wrreq"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="fifo_output" altera:internal="fifo_0.fifo_output" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="empty" altera:internal="empty"></altera:port_mapping>
+ <altera:port_mapping altera:name="full" altera:internal="full"></altera:port_mapping>
+ <altera:port_mapping altera:name="q" altera:internal="q"></altera:port_mapping>
+ <altera:port_mapping altera:name="usedw" altera:internal="usedw"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.vhd b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b9b6939f7050fc561ae21439b2644fbea13caa4a
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.vhd
@@ -0,0 +1,108 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper / Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_sc_fifo_1921_7egef6q.vhd
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library altera_mf;
+use altera_mf.all;
+
+entity ip_agi027_xxxx_fifo_sc is
+ generic (
+ g_use_eab : string := "ON";
+ g_dat_w : natural := 20;
+ g_nof_words : natural := 1024
+ );
+ port (
+ aclr : in std_logic;
+ clock : in std_logic;
+ data : in std_logic_vector(g_dat_w - 1 downto 0);
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
+ usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+end ip_agi027_xxxx_fifo_sc;
+
+architecture SYN of ip_agi027_xxxx_fifo_sc is
+ component scfifo
+ generic (
+ add_ram_output_register : string;
+ -- enable_ecc : string;
+ intended_device_family : string;
+ lpm_numwords : natural;
+ lpm_showahead : string;
+ lpm_type : string;
+ lpm_width : natural;
+ lpm_widthu : natural;
+ overflow_checking : string;
+ underflow_checking : string;
+ use_eab : string
+ );
+ port (
+ aclr : in std_logic;
+ clock : in std_logic;
+ data : in std_logic_vector(g_dat_w - 1 downto 0);
+ rdreq : in std_logic;
+ wrreq : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ q : out std_logic_vector(g_dat_w - 1 downto 0);
+ usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+ end component;
+begin
+ u_scfifo : scfifo
+ generic map (
+ add_ram_output_register => "ON",
+ -- enable_ecc => "FALSE",
+ intended_device_family => "Agilex 7",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "scfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => g_use_eab
+ )
+ port map (
+ aclr => aclr,
+ clock => clock,
+ data => data,
+ rdreq => rdreq,
+ wrreq => wrreq,
+ empty => empty,
+ full => full,
+ q => q,
+ usedw => usedw
+ );
+end SYN;