-Added apertif_unb1_correlator which is unb1_correlator copied and renamed.

applications/apertif_unb1_correlator/hdllib.cfg

+hdl_lib_name = apertif_unb1_correlator
+hdl_library_clause_name = apertif_unb1_correlator_lib
+hdl_lib_uses = common mm i2c unb1_board correlator 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_top_level_entity =
+
+quartus_copy_files =
+    quartus/qsys_apertif_unb1_correlator.qsys .
+
+synth_files =
+    $HDL_BUILD_DIR/quartus/apertif_unb1_correlator/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
+    src/vhdl/mmm_apertif_unb1_correlator.vhd
+    src/vhdl/apertif_unb1_correlator.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_apertif_unb1_correlator.vhd
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    
+quartus_tcl_files =
+    quartus/apertif_unb1_correlator_pins.tcl
+    
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/quartus/apertif_unb1_correlator/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.qip

applications/apertif_unb1_correlator/quartus/apertif_unb1_correlator_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+

applications/apertif_unb1_correlator/src/vhdl/unb1_apertif_correlator.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, correlator_lib, diag_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY apertif_unb1_correlator IS
+  GENERIC (
+    g_design_name : STRING  := "apertif_unb1_correlator";
+    g_sim         : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_unb_nr  : NATURAL := 0;
+    g_sim_node_nr : NATURAL := 0;
+    g_stamp_date  : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time  : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_stamp_svn   : NATURAL := 0   -- SVN revision    -- set by QSF
+  );
+  PORT (
+    -- GENERAL
+    CLK          : IN    STD_LOGIC; -- System Clock
+    PPS          : IN    STD_LOGIC; -- System Sync
+    WDI          : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA         : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB         : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION      : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+    ID           : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+    TESTIO       : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+    
+    -- I2C Interface to Sensors
+    sens_sc      : INOUT STD_LOGIC;
+    sens_sd      : INOUT STD_LOGIC;
+  
+    -- 1GbE Control Interface
+    ETH_clk      : IN    STD_LOGIC;
+    ETH_SGIN     : IN    STD_LOGIC;
+    ETH_SGOUT    : OUT   STD_LOGIC
+  );
+END apertif_unb1_correlator;
+
+
+ARCHITECTURE str OF apertif_unb1_correlator IS
+
+  -- Firmware version x.y
+  CONSTANT c_fw_version             : t_unb1_board_fw_version := (1, 1);
+  -- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
+  CONSTANT c_use_phy                : t_c_unb1_board_use_phy  := (sel_a_b(g_sim, 0, 1), 0, 0, 0, 0, 0, 0, 1);
+
+  -- System
+  SIGNAL cs_sim                     : STD_LOGIC;
+  SIGNAL xo_clk                     : STD_LOGIC;
+  SIGNAL xo_rst                     : STD_LOGIC;
+  SIGNAL xo_rst_n                   : STD_LOGIC;
+  SIGNAL mm_clk                     : STD_LOGIC;
+  SIGNAL mm_locked                  : STD_LOGIC;
+  SIGNAL mm_rst                     : STD_LOGIC;
+  
+  SIGNAL dp_rst                     : STD_LOGIC;
+  SIGNAL dp_clk                     : STD_LOGIC;
+  
+  -- PIOs
+  SIGNAL pout_wdi                   : STD_LOGIC;
+
+  -- WDI override
+  SIGNAL reg_wdi_mosi               : t_mem_mosi;
+  SIGNAL reg_wdi_miso               : t_mem_miso;
+
+  -- PPSH
+  SIGNAL reg_ppsh_mosi              : t_mem_mosi;
+  SIGNAL reg_ppsh_miso              : t_mem_miso;
+  
+  -- UniBoard system info
+  SIGNAL reg_unb_system_info_mosi   : t_mem_mosi;
+  SIGNAL reg_unb_system_info_miso   : t_mem_miso;
+  SIGNAL rom_unb_system_info_mosi   : t_mem_mosi;
+  SIGNAL rom_unb_system_info_miso   : t_mem_miso;
+
+  -- UniBoard I2C sens
+  SIGNAL reg_unb_sens_mosi          : t_mem_mosi;
+  SIGNAL reg_unb_sens_miso          : t_mem_miso;
+
+  -- eth1g
+  SIGNAL eth1g_tse_clk              : STD_LOGIC;
+  SIGNAL eth1g_mm_rst               : STD_LOGIC;
+  SIGNAL eth1g_tse_mosi             : t_mem_mosi;  -- ETH TSE MAC registers
+  SIGNAL eth1g_tse_miso             : t_mem_miso;
+  SIGNAL eth1g_reg_mosi             : t_mem_mosi;  -- ETH control and status registers
+  SIGNAL eth1g_reg_miso             : t_mem_miso;
+  SIGNAL eth1g_reg_interrupt        : STD_LOGIC;   -- Interrupt
+  SIGNAL eth1g_ram_mosi             : t_mem_mosi;  -- ETH rx frame and tx frame memory
+  SIGNAL eth1g_ram_miso             : t_mem_miso;
+
+  -- Correlator
+  CONSTANT c_nof_inputs             : NATURAL := 24;
+  CONSTANT c_nof_pre_mult_folds     : NATURAL := 1; 
+  CONSTANT c_complex_data_w         : NATURAL := 8;
+  CONSTANT c_conjugate              : BOOLEAN := TRUE;
+  CONSTANT c_nof_channels           : NATURAL := 64;
+  CONSTANT c_integration_period     : NATURAL := 12208;
+
+  CONSTANT c_nof_visibilities       : NATURAL := (c_nof_inputs*(c_nof_inputs+1))/2;
+
+  -- Gap size on the correlator input depends on the number of folds
+  CONSTANT c_block_period           : NATURAL := pow2(c_nof_pre_mult_folds);
+
+  -- Block generator
+  CONSTANT c_bg_block_size          : NATURAL := c_nof_channels;
+  CONSTANT c_bg_gapsize             : NATURAL := c_bg_block_size*(c_block_period-1);
+
+  -- Indicate the integration period with the sync. In the correlator, the
+  -- integration period is forced to a minimum of c_nof_visibilities to
+  -- allow folding the output onto one stream.
+  -- . The sync pulse is only there for the human eye (wave window) -
+  --   it is not used by the correlator.
+  CONSTANT c_bg_blocks_per_sync     : NATURAL := largest(c_integration_period, c_nof_visibilities);
+
+  CONSTANT c_bg_ctrl                : t_diag_block_gen := ('1',                      -- enable             
+                                                           '0',                      -- enable_sync        
+                                                          TO_UVEC(     c_bg_block_size, c_diag_bg_samples_per_packet_w),
+                                                          TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+                                                          TO_UVEC(        c_bg_gapsize, c_diag_bg_gapsize_w),
+                                                          TO_UVEC(                   0, c_diag_bg_mem_low_adrs_w),
+                                                          TO_UVEC(   c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+                                                          TO_UVEC(                   0, c_diag_bg_bsn_init_w));
+
+  SIGNAL block_gen_src_out_arr      : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
+
+  SIGNAL dp_fifo_sc_src_out_arr     : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
+  SIGNAL dp_fifo_sc_src_in_arr      : t_dp_siso_arr(c_nof_inputs-1 DOWNTO 0);
+
+  SIGNAL correlator_snk_in_arr      : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
+  SIGNAL correlator_src_out_arr     : t_dp_sosi_arr(1-1 DOWNTO 0);
+
+  SIGNAL ram_diag_data_buf_mosi     : t_mem_mosi;
+  SIGNAL ram_diag_data_buf_miso     : t_mem_miso;
+  SIGNAL reg_diag_data_buf_mosi     : t_mem_mosi;
+  SIGNAL reg_diag_data_buf_miso     : t_mem_miso; 
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- Block generators
+  -- . Each stream in block_gen_src_out_arr contains complex subband samples
+  --   from one 'antenna'.
+  -- . These complex subband samples are generated and converted to a HEX RAM
+  --   initialization file using Python, see tb/python/gen_subband_hex_files.py
+  -----------------------------------------------------------------------------
+  u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
+  GENERIC MAP (
+    g_nof_output_streams => c_nof_inputs,
+    g_buf_dat_w          => 2*c_complex_data_w,
+    g_buf_addr_w         => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+    g_file_name_prefix   => "../../../libraries/dsp/correlator/src/hex/complex_subbands_" & NATURAL'IMAGE(c_complex_data_w),
+    g_diag_block_gen_rst => c_bg_ctrl
+  )
+  PORT MAP (
+    mm_rst           => mm_rst,
+    mm_clk           => mm_clk,
+
+    dp_rst           => dp_rst,
+    dp_clk           => dp_clk,
+
+    out_sosi_arr     => block_gen_src_out_arr
+  );
+
+  -----------------------------------------------------------------------------
+  -- Introduce gaps in the input stream
+  -- . mms_diag_block_gen does not support gaps within blocks.
+  -- . We'll use FIFO buffers and dp_gap to read out the FIFOs to introduce
+  --   gaps.
+  -----------------------------------------------------------------------------
+  gen_dp_fifo_sc : FOR i IN 0 TO c_nof_inputs-1 GENERATE
+    u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+    GENERIC MAP (
+      g_data_w         => 2*c_complex_data_w,
+      g_use_ctrl       => FALSE,
+      g_use_complex    => TRUE,
+      g_fifo_size      => c_nof_channels,
+      g_fifo_af_margin => 0
+    )
+    PORT MAP (
+      rst         => dp_rst,
+      clk         => dp_clk,
+
+      wr_ful      => OPEN,
+      usedw       => OPEN,
+      rd_emp      => OPEN,
+
+      snk_out     => OPEN,
+      snk_in      => block_gen_src_out_arr(i),
+      src_in      => dp_fifo_sc_src_in_arr(i),
+      src_out     => dp_fifo_sc_src_out_arr(i)
+    );
+  END GENERATE;
+
+  gen_dp_src_out_timer : FOR i IN 0 TO c_nof_inputs-1 GENERATE
+    u_dp_src_out_timer : ENTITY dp_lib.dp_src_out_timer
+    GENERIC MAP (
+      g_block_period => c_block_period
+    )
+    PORT MAP (
+      rst                  => dp_rst,
+      clk                  => dp_clk,
+
+      snk_in               => dp_fifo_sc_src_out_arr(i),
+      snk_out              => dp_fifo_sc_src_in_arr(i)
+    );
+  END GENERATE;
+
+  correlator_snk_in_arr <= dp_fifo_sc_src_out_arr;
+
+  -----------------------------------------------------------------------------
+  -- Correlator
+  -----------------------------------------------------------------------------
+  u_correlator : ENTITY correlator_lib.correlator
+  GENERIC MAP (
+    g_nof_inputs         => c_nof_inputs,
+    g_nof_pre_mult_folds => c_nof_pre_mult_folds,
+    g_data_w             => c_complex_data_w,
+    g_conjugate          => c_conjugate,
+    g_nof_channels       => c_nof_channels,
+    g_integration_period => c_integration_period
+  )
+  PORT MAP (
+    clk         => dp_clk,
+    rst         => dp_rst,
+
+    snk_in_arr  => correlator_snk_in_arr,
+    src_out_arr => correlator_src_out_arr
+  );
+
+  -----------------------------------------------------------------------------
+  -- Data buffer to be read out by Python
+  -----------------------------------------------------------------------------
+  u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+  GENERIC MAP (    
+    g_nof_streams  => 1,
+    g_data_w       => 64,
+    g_data_type    => e_complex,
+    g_buf_nof_data => c_nof_visibilities,
+    g_buf_use_sync => TRUE 
+  )
+  PORT MAP (
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    dp_rst            => dp_rst,
+    dp_clk            => dp_clk,
+
+    ram_data_buf_mosi => ram_diag_data_buf_mosi,
+    ram_data_buf_miso => ram_diag_data_buf_miso,
+    reg_data_buf_mosi => reg_diag_data_buf_mosi,
+    reg_data_buf_miso => reg_diag_data_buf_miso,
+
+    in_sync           => correlator_src_out_arr(0).sop,
+    in_sosi_arr       => correlator_src_out_arr
+  );
+
+  -----------------------------------------------------------------------------
+  -- General control function
+  -----------------------------------------------------------------------------
+  u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
+  GENERIC MAP (
+    g_sim         => g_sim,
+    g_design_name => g_design_name,
+    g_stamp_date  => g_stamp_date,
+    g_stamp_time  => g_stamp_time, 
+    g_stamp_svn   => g_stamp_svn, 
+    g_fw_version  => c_fw_version,
+    g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+    g_use_phy     => c_use_phy,
+    g_aux         => c_unb1_board_aux,
+    g_dp_clk_use_pll => FALSE -- Use altpll_1 in QSYS
+  )
+  PORT MAP (
+    -- Clock an reset signals
+    cs_sim                   => cs_sim,
+    xo_clk                   => xo_clk,
+    xo_rst                   => xo_rst,
+    xo_rst_n                 => xo_rst_n,
+
+    mm_clk                   => mm_clk,
+    mm_locked                => mm_locked,
+    mm_rst                   => mm_rst,
+
+    epcs_clk                 => '0',
+    
+    dp_rst                   => dp_rst,
+    dp_clk                   => OPEN, --dp_clk,
+    dp_pps                   => OPEN,
+    dp_rst_in                => dp_rst,
+    dp_clk_in                => dp_clk,
+    
+    -- Toggle WDI
+    pout_wdi                 => pout_wdi,
+
+    -- MM buses
+    -- . Manual WDI override
+    reg_wdi_mosi             => reg_wdi_mosi,
+    reg_wdi_miso             => reg_wdi_miso,
+    
+    -- . System_info
+    reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+    reg_unb_system_info_miso => reg_unb_system_info_miso, 
+    rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+    rom_unb_system_info_miso => rom_unb_system_info_miso, 
+    
+    -- . UniBoard I2C sensors
+    reg_unb_sens_mosi        => reg_unb_sens_mosi,
+    reg_unb_sens_miso        => reg_unb_sens_miso,    
+    
+    -- . PPSH
+    reg_ppsh_mosi            => reg_ppsh_mosi,
+    reg_ppsh_miso            => reg_ppsh_miso,
+
+    -- eth1g
+    eth1g_tse_clk            => eth1g_tse_clk,   -- 125 MHz from xo_clk PLL in SOPC system
+    eth1g_mm_rst             => eth1g_mm_rst,
+    eth1g_tse_mosi           => eth1g_tse_mosi,
+    eth1g_tse_miso           => eth1g_tse_miso,
+    eth1g_reg_mosi           => eth1g_reg_mosi,
+    eth1g_reg_miso           => eth1g_reg_miso,
+    eth1g_reg_interrupt      => eth1g_reg_interrupt,
+    eth1g_ram_mosi           => eth1g_ram_mosi,
+    eth1g_ram_miso           => eth1g_ram_miso,
+        
+    -- FPGA pins
+    -- . General
+    CLK                      => '0',
+    PPS                      => PPS,
+    WDI                      => WDI,
+    INTA                     => INTA,
+    INTB                     => INTB,
+    -- . Others
+    VERSION                  => VERSION,
+    ID                       => ID,
+    TESTIO                   => TESTIO,
+    -- . I2C Interface to Sensors
+    sens_sc                  => sens_sc,
+    sens_sd                  => sens_sd,        
+    -- . 1GbE Control Interface
+    ETH_clk                  => ETH_clk,
+    ETH_SGIN                 => ETH_SGIN,
+    ETH_SGOUT                => ETH_SGOUT
+  );
+
+  -----------------------------------------------------------------------------
+  -- MM master
+  -----------------------------------------------------------------------------
+  u_mmm : ENTITY work.mmm_apertif_unb1_correlator
+  GENERIC MAP (
+    g_sim         => g_sim,
+    g_sim_unb_nr  => g_sim_unb_nr,
+    g_sim_node_nr => g_sim_node_nr
+   )
+  PORT MAP(  
+    xo_clk                   => xo_clk,       
+    xo_rst_n                 => xo_rst_n,     
+    xo_rst                   => xo_rst,       
+
+    mm_rst                   => mm_rst,
+    mm_clk                   => mm_clk,       
+    mm_locked                => mm_locked,    
+
+    clk_clk                  => CLK, -- altpll_1 ref clk (200MHz)
+    clk_clk_in_reset_reset_n => xo_rst_n,
+    altpll_1_c0_clk          => dp_clk, -- altpll_1 output clock
+
+    -- PIOs
+    pout_wdi                 => pout_wdi,
+
+    -- Manual WDI override
+    reg_wdi_mosi             => reg_wdi_mosi,
+    reg_wdi_miso             => reg_wdi_miso,
+
+    -- system_info
+    reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+    reg_unb_system_info_miso => reg_unb_system_info_miso,
+    rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+    rom_unb_system_info_miso => rom_unb_system_info_miso, 
+
+    -- UniBoard I2C sensors
+    reg_unb_sens_mosi        => reg_unb_sens_mosi,
+    reg_unb_sens_miso        => reg_unb_sens_miso, 
+ 
+    -- PPSH
+    reg_ppsh_mosi            => reg_ppsh_mosi,
+    reg_ppsh_miso            => reg_ppsh_miso, 
+
+    -- . Data buffers
+    reg_diag_data_buf_mosi   => reg_diag_data_buf_mosi,
+    reg_diag_data_buf_miso   => reg_diag_data_buf_miso,
+
+    ram_diag_data_buf_mosi   => ram_diag_data_buf_mosi,
+    ram_diag_data_buf_miso   => ram_diag_data_buf_miso,    
+  
+    -- eth1g
+    eth1g_tse_clk            => eth1g_tse_clk,
+    eth1g_mm_rst             => eth1g_mm_rst,
+    eth1g_tse_mosi           => eth1g_tse_mosi,
+    eth1g_tse_miso           => eth1g_tse_miso,
+    eth1g_reg_mosi           => eth1g_reg_mosi,
+    eth1g_reg_miso           => eth1g_reg_miso,
+    eth1g_reg_interrupt      => eth1g_reg_interrupt,
+    eth1g_ram_mosi           => eth1g_ram_mosi,
+    eth1g_ram_miso           => eth1g_ram_miso
+  );
+
+END str;
+

applications/apertif_unb1_correlator/tb/vhdl/tb_apertif_unb1_correlator.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- Description:
+-- Usage:
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_apertif_unb1_correlator IS
+END tb_apertif_unb1_correlator;
+
+ARCHITECTURE tb OF tb_apertif_unb1_correlator IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 7; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb1_board_fw_version := (1, 0);
+
+  CONSTANT c_cable_delay     : TIME := 12 ns;
+  CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
+  CONSTANT c_clk_period      : TIME := 5 ns; 
+  CONSTANT c_pps_period      : NATURAL := 1000; 
+
+  -- DUT
+  SIGNAL clk                 : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC;
+  SIGNAL eth_rxp             : STD_LOGIC;
+  
+  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version; 
+  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)      := c_id;
+  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
+  
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+  
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_apertif_unb1_correlator : ENTITY work.apertif_unb1_correlator
+    GENERIC MAP (
+      g_sim         => c_sim,
+      g_sim_unb_nr  => c_unb_nr,
+      g_sim_node_nr => c_node_nr
+    )
+    PORT MAP (
+      -- GENERAL
+      CLK         => clk,
+      PPS         => pps,
+      WDI         => WDI,
+      INTA        => INTA,
+      INTB        => INTB,
+
+      sens_sc     => sens_scl,
+      sens_sd     => sens_sda,
+
+      -- Others
+      VERSION     => VERSION,
+      ID          => ID,
+      TESTIO      => TESTIO,
+
+      -- 1GbE Control Interface
+      ETH_clk     => eth_clk,
+      ETH_SGIN    => eth_rxp,
+      ETH_SGOUT   => eth_txp
+    );
+
+END tb;